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PDF DP83924 Data sheet ( Hoja de datos )
| Número de pieza | DP83924 | |
| Descripción | Quad 10 Mb/s Ethernet Physical Layer - 4TPHY | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 1998
DP83924BVCE
Quad 10 Mb/s Ethernet Physical Layer - 4TPHY™
General Description
The DP83924B Quad 10Mbps Ethernet Physical Layer
(4TPHY) is a 4-Port Twisted Pair PHYsical Layer Trans-
ceiver that includes all the circuitry required to interface
four Ethernet Media Access Controllers (MACs) to
10BASE-T. This device is ideally suited for switch hub
applications where 8 to 32 ports are commonly used.
The 4TPHY has three dedicated 10Base-T ports. There is
an additional port that is selectable for either 10Base-T or
for an Attachment Unit Interface (AUI). In 10Base-T mode,
any port can be configured to be Half or Full Duplex.
(Continued)
Features
s 100 pin package
s 10BASE-T and AUI interfaces
s Automatic or manual selection of twisted pair or Attach-
ment Unit Interfaces on port 1
s Direct Interface to NRZ Compatible controllers
s IEEE 802.3u Auto-Negotiation between 10Mb/s Full
and Half Duplex data traffic and parallel detection
s MII-like Serial management interface for configuration
and monitoring of ENDEC/Transceiver operation.
s Programmable MAC Interface supports most
standard 7 signal MAC interfaces
s Twisted Pair Transceiver Module
– On-chip filters for transmit outputs
– Low Power Driver
– Heartbeat and Jabber Timers
– Link Disable and Smart Receive Squelch
– Polarity detection and correction
– Jabber Enable/Disable
– Isolate mode for diagnostics
– Low Power Class AB Attachment Unit Interface (AUI)
Driver for one port
– Enhanced Supply Rejection
– Enhanced Jitter Performance
– Diagnostic Endec Loopback
– Squelch on Collision and Receive Pair
s Serial LED interface for LINK, POLARITY, ACTIVITY,
and ERROR.
s JTAG Boundary Scan per IEEE 1149.1
System Diagram
MAC Serial
NRZ Interface
10BASE-T
10BASE-2
TPI
ports 1-4
DP83924B
AUI
(port 1 option)
RXD4,RXC4,COL4,CRS4
TXD4,TXE4
RXD3,RXC3,COL3,CRS3
TXD3,TXE3
RXD2,RXC2,COL2,CRS2
TXD2,TXE2
RXD1,RXC1,COL1,CRS1
TXD1,TXE1
TXC
MDIO MDC
Serial Mgmt Interface
4TPHY™ is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
MAC
www.national.com
1 page  
1.0 Pin Information (Continued)
1.2 Pin Description
Table 1. NRZ CONTROLLER INTERFACE and MANAGEMENT INTERFACE.
These pins provide the interface signalling between the Media Access Controller and the transceiver. (30 Pins)
Symbol Pin # Type
Description
TXC
77 O Transmit Clock: This pin outputs a 10 MHz output clock signal synchronized to the
transmit data (for all ports).
TXD[4]
TXD[3]
TXD[2]
TXD[1]
40
46
56
71
I Transmit Data: The serial TXD contains the transmit serial data output stream.
TXE[4]
TXE[3]
TXE[2]
TXE[1]
41
47
57
72
I Transmit Enable: This active high input indicates the presence of valid data on the TXD
pins.
CRS[4]
CRS[3]
CRS[2]
CRS[1]
43 O, pull-up Carrier Sense: Active high output indicates that valid data has been detected on the
52 O, pull-up receive inputs.
59
74
O, pull-up
O, pull-up
CRS[3:1] are dual purpose pins. When RESET is active, the value on these pins are
sampled to determine the transceiver address for the mgmt interface. These pins have
internal pull-ups, a 2.7 kΩ pull down resistor is required to program a logic ‘0’.
COL[4]
COL[3]
COL[2]
COL[1]
44 O, pull-up Collision: This active high output is asserted when a collision condition has been de-
54 O, pull-up tected. It is also asserted for 1µs at the end of a packet to indicate the SQE test function.
60
75
O, pull-up
O, pull-up
COL[4:1] are dual purpose pins. When RESET is active, these pins are sampled and
selects the operating mode for the device. These pins have internal pull-ups to select
the default mode if no external pull-downs are connected. To select the non-default
mode(s), a 2.7 kΩ pull down resistor(s) is required. The strappable functions are:
COL[4]; selects the number of receive clocks after carrier sense deassertion (5 RXCs
or continuous RXCs). Default is 5 RXCs.
COL[3]; enables or disables the receive filter. Default is to disable the receive filter.
COL[2]; Disables Management Interface and selects the Full Duplex operating mode
(normal or enhanced). Default is normal full duplex mode. If the enhanced Full- Duplex
mode is selected, the functions of pins 89, 90, 92, 93, and 94 are also changed. See
the descriptions in Sectio n3.3.13 and Se ction3.3.14.
COL[1]; selects the LED operating mode (normal or enhanced). Default is normal LED
mode.
RXC[4]
RXC[3]
RXC[2]
RXC[1]
45
55
61
76
O Receive Clock: This 10 MHz signal is generated by the transceiver, and is the recov-
ered clock from the decoded network data stream. This signal is 10 MHz.
The number of RXCs after the deassertion of CRS is programmable via the Global Con-
figuration Register, GATERXC bit, D0. The options are for 5 RXCs or continuous RXCs.
RXD[4]
RXD[3]
RXD[2]
RXD[1]
42 O, Pull-up Receive Data: Provides the decoded receive serial data. Data is valid on the risin
51 edge of RXC.
58
73
RXD[4:1] are dual purpose pins. When RESET is active, these pins are sampled and
selects the operating mode for the device. These pins have internal pull-ups to select
the default mode if no external pull-downs are connected. To select the non-default
mode(s), a 2.7 kΩ pull down resistor(s) is required. The strappable functions are:
RXD[4] enables/disables Auto-Negotiation.
RXD[3:1] selects one of five MAC interface modes. See the table in the Interface De-
scriptions section.
MDC
93 I Management Data Clock: When management interface is enabled (strap option,
LPBK
COL[2]=1), this clock signal (0-2.5MHz) is the clock for transferring data across the
management interface.
LoopBack: When “Disable Management Interface” mode is selected (strap option,
COL[2]=0), then this pin is an active high input to configure all ports into diagnostic loop-
back mode.
5 www.national.com
5 Page 
2.0 Interface Descriptions (Continued)
Table 7. MAC Interface Selection
Parameter
RXCs Active
Mode 1
Mode 2
Mode 3
CRS + 5 clks CRS asserteda Continuous
Mode 4
Continuous
Edge of TXc that TXD is sampled
Rising
Rising
Falling
Falling
Polarity of active TXE
High
Edge of RXC that RXD is clocked
Rising
Polarity of CRS asserted
High
Level of RXD during CRS deassertion Low
Polarity of active COL
High
Polarity of active Loopback (LPBK) High
High
Rising
High
High
High
High
High
Rising
High
Low
High
Low
High
Falling
High
Low
Low
High
How to select MAC interface modeb
Using registers to select mode
Global Control & Status Register
111
001
010
(GCSR, addr 08H) bits D[8:6]
GCSR bit D[4] (select RXD_Idle level) 0 1 0
011
0
GCSR bit D[0] (select RXC modec) 1 1 0 0
Using strap options to select mode
RXD[3:1] strap option
(same as GCSR D[8:6])
111 001 010 011
LINK[1] strap option (RXD idle level) 1 0 1 1
COL[4] strap option (RXC mode)
1
1
0
0
a. No extra clocks are added after CRS. (CRS + 0 clocks RXC mode)
b. The mode can be selected by either strap options or writing to the registers. The default for
both is NSC,TI.
c. GCSR D[0] or COL[4] strap can’t be used to select CRS + 0 clocks RXC mode. This mode is
selected by the GCSR bits D[8:6] or RXD[3:1] strap option.
Table 8. Normal LED Mode
LED Condition
Off
Status Indication
Good Status
On - Solid
Error Statusa
Fast Blink (400 ms)
Slow Blink (1600 ms)
Link Lost
Bad Polarity
a. Bit 7 of registers 00-03 can be set by the user
/management entity based on any criteria they
choose and will be used to turn on Error Status
LED.
Table 9. Enhanced LED Mode - Bit Decode
FDX
0
0
LinkCoded
0
1
LED Status
OFF
ON - Color A
Comments
Link Fail, Full
Duplex
Good Link, Full
Duplex
1 0 ON - Color B Good Link, Half
Duplex
11
OFF
Link Fail, Half
Duplex
If the standard 78 ohm transceiver cable is used, the
receive differential input must be externally terminated with
two 39 ohm resistors connected in series. In thin Ethernet
applications, these resistors are optional. To prevent noise
from falsely triggering the decoder, a squelch circuit at the
input rejects signals with levels less than + 160mV. Signals
with levels greater than + 300 mV are decoded.
If the AUI interface is not used, the unused AUI inputs can
be left floating or the +/- inputs could be shorted to each
other and the unused AUI outputs should be left floating.
2.4.3 Oscillator Clock
When using an oscillator, additional output drive may be
necessary if the oscillator must also drive other compo-
nents. The X1 pin is a simple TTL compatible input. See
Figur e8.
11 www.national.com
11 Page | ||
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| PDF Descargar | [ Datasheet DP83924.PDF ] | |
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