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PDF MACH111SP Data sheet ( Hoja de datos )

Número de pieza MACH111SP
Descripción High-Performance EE CMOS Programmable Logic
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo



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No Preview Available ! MACH111SP Hoja de datos, Descripción, Manual

MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmable Logic
FEATURES
x High-performance electrically-erasable CMOS PLD families
x 32 to 128 macrocells
x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages
x SpeedLocking™ – guaranteed fixed timing up to 16 product terms
x Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD
x Configurable macrocells
— Programmable polarity
— Registered or combinatorial outputs
— Internal and I/O feedback paths
— D-type or T-type flip-flops
— Output Enables
— Choice of clocks for each flip-flop
— Input registers for MACH 2 family
x JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available
x Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns
x Safe for mixed supply voltage system designs
x Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs
x Programmable power-down mode results in power savings of up to 75%
x Supported by Vantis DesignDirect™ software for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
x Lattice/Vantis and third-party hardware programming support
— Lattice/VantisPRO™ (formerly known as MACHPRO®) software for in-system programmability
support on PCs and Automated Test Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication# 14051 Rev: K
Amendment/0
Issue Date: November 1998

1 page




MACH111SP pdf
Each PAL block consists of the following elements:
x Product-term array
x Logic Allocator
x Macrocells
x I/O cells
Each PAL block additionally contains an asynchronous reset product term and an asynchronous
preset product term. This allows the flip-flops within a single PAL block to be initialized as a bank.
There are also output enable product terms that provide tri-state control for the I/O cells.
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic being
implemented. The inputs to the AND gates come from the switch matrix (Table 4), and are
provided in both true and complement forms for efficient logic implementation.
Because the number of product terms available for a given function is not fixed, the full sum of
products is not realized in the array. The product terms drive the logic allocator, which allocates
the appropriate number of product terms to generate the function.
Table 4. PAL Block Inputs
Device
MACH111
MACH111SP
MACH131
MACH131SP
MACH211
Number of Inputs to PAL Block
26
26
26
26
26
Device
MACH211SP
MACH221
MACH221SP
MACH231
MACH231SP
Number of Inputs to PAL Block
26
26
26
32
32
Logic Allocator
The logic allocator (Figure 2) is a block within which different product terms are allocated to the
appropriate macrocells in groups of four product terms called “product term clusters”. The
availability and distribution of product term clusters is automatically considered by the software as
it fits functions within the PAL block. The size of the product term clusters has been designed to
provide high utilization of product terms. Complex functions using many product terms are
possible, and when few product terms are used, there will be a minimal number of unused, or
wasted, product terms left over.
The product term clusters do not “wrap” around the logic block. This means that the macrocells
at the ends of the block have fewer product terms available (Tables 5, 6, 7, 8).
MACH 1 & 2 Families
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MACH111SP arduino
The flip-flops in either macrocell type can be clocked by one of several clock pins (Table 10).
Registers are clocked on the rising edge of the clock input. Latches hold their data when the gate
input is HIGH. Clock pins are also available as inputs, although care must be taken when a signal
acts as both clock and input to the same device.
Table 10. Macrocell Clocks
Device
MACH111
MACH111SP
MACH131
MACH131SP
MACH211
Number of Clocks Available
4
2
4
4
4
Device
MACH211SP
MACH221
MACH221SP
MACH231
MACH231SP
Number of Clocks Available
2
4
4
4
4
All flip-flops have asynchronous reset and preset. This is controlled by the common product terms
that control all flip-flops within a PAL block. For a single PAL block, all flip-flops, whether in an
output or a buried macrocell, are initialized together. The initialization functionality of the flip-flops
is illustrated in Table 11.
Table 11. Asynchronous Reset/Preset Operation
Configuration
Register
Latch
AR AP
00
01
10
11
00
01
01
10
10
11
11
CLK/LE
X
X
X
X
X
0
1
0
1
0
1
Q+
See Table 9
1
0
0
See Table 9
Illegal
1
Illegal
0
Illegal
0
I/O Cells
The I/O cells (Figure 7) provide a three-state output buffer. The three-state buffer can be left
permanently enabled for use only as an output, permanently disabled for use as an input, or it can
be controlled by one of two product terms for bi-directional signals and bus connections. The two
product terms provided are common to a bank of I/O cells.
MACH 1 & 2 Families
11

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