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PDF SCC2692 Data sheet ( Hoja de datos )
| Número de pieza | SCC2692 | |
| Descripción | Dual asynchronous receiver/transmitter DUART | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
SCC2692
Dual asynchronous receiver/transmitter
(DUART)
Product specification
Supersedes data of 1998 Feb 19
IC19 Data Handbook
1998 Sep 04
Philips
Semiconductors
1 page  
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCC2692
PIN DESCRIPTION
APPLICABLE
SYMBOL
40,44 28
D0-D7
X
X
CEN
XX
WRN
RDN
A0-A3
RESET
X
X
X
X
X
X
X
X
INTRN
X1/CLK
X2
RxDA
RxDB
TxDA
X
X
X
X
X
X
X
X
X
X
X
X
TxDB X X
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
IP0
IP1
IP2
IP3
XX
XX
X
X
X
X
X
X
X
X
XX
X
IP4 X
IP5 X
IP6 X
VCC
XX
GND X X
TYPE
I/O
I
I
I
I
I
O
I
I
I
I
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
NAME AND FUNCTION
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the
DUART and the CPU. D0 is the least significant bit.
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART
are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the
D0-D7 lines in the 3-State condition.
Write Strobe: When Low and CEN is also Low, the contents of the data bus are loaded into the
addressed register. The transfer occurs on the rising edge of the signal.
Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on the falling edge of RDN.
Address Inputs: Select the DUART internal registers and ports for read/write operations.
Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in
the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA
and TxDB outputs in the mark (High) state. Resets Test modes, MR pointer set to MR1.
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the
eight maskable interrupting conditions are true.
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.
Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not
connected although it is permissible to ground it.
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High,
“space” is Low.
Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High,
“space” is Low.
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback
mode. “Mark” is High, “space” is Low.
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output
is held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local
loopback mode. ‘Mark’ is High, ‘space’ is Low.
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A
receiver 1X clock output.
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B
transmitter 1X clock output, or Channel B receiver 1X clock output.
Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYAN/FFULLAN output.
Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYBN/FFULLBN output.
Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYAN output.
Output 7: General purpose output, or Channel B open-drain, active-Low, TxRDYBN output.
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an
internal VCC pull-up device supplying 1 to 4 mA of current.
Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an
internal VCC pull-up device supplying 1 to 4 mA of current.
Input 2: General purpose input or counter/timer external clock input. Pin has an internal VCC pull-up
device supplying 1 to 4 mA of current.
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current.
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 mA of current.
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current.
Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 mA of current.
Power Supply: +5V supply input.
Ground
1998 Sep 04
5
5 Page 
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCC2692
Table 1. SCC2692 Register Addressing
A3 A2 A1 A0
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1
READ (RDN = 0)
Mode Register A (MR1A, MR2A)
Status Register A (SRA)
BRG Test
Rx Holding Register A (RHRA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Counter/Timer Upper Value (CTU)
Counter/Timer Lower Value (CTL)
Mode Register B (MR1B, MR2B)
Status Register B (SRB)
1X/16X Test
Rx Holding Register B (RHRB)
Reserved
Input Ports IP0 to IP6
Start Counter Command
Stop Counter Command
WRITE (WRN = 0)
Mode Register A (MR1A, MR2A)
Clock Select Register A (CSRA)
Command Register A (CRA)
Tx Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
C/T Upper Preset Value (CRUR)
C/T Lower Preset Value (CTLR)
Mode Register B (MR1B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
Tx Holding Register B (THRB)
Reserved
Output Port Conf. Register (OPCR)
Set Output Port Bits Command
Reset Output Port Bits Command
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
Table 2. Register Bit Formats
BIT 7
BIT 6
MR1A
MR1B
RxRTS
CONTROL
0 = No
1 = Yes
RxINT
SELECT
0 = RxRDY
1 = FFULL
BIT 5
ERROR
MODE*
0 = Char
1 = Block
BIT 4
BIT 3
PARITY MODE
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
BIT 2
PARITY
TYPE
0 = Even
1 = Odd
BIT 1
BIT 0
BITS PER
CHARACTER
00 = 5
01 = 6
10 = 7
11 = 8
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
BIT 7
BIT 6
BIT 5
BIT 4
MR2A
MR2B
CHANNEL MODE
00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
TxRTS
CONTROL
0 = No
1 = Yes
CTS
ENABLE Tx
0 = No
1 = Yes
NOTE: *Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
BIT 3
0 = 0.563
1 = 0.625
2 = 0.688
3 = 0.750
BIT 2
BIT 1
STOP BIT LENGTH*
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
8 = 1.563
9 = 1.625
A = 1.688
B = 1.750
BIT 0
C = 1.813
D = 1.875
E = 1.938
F = 2.000
CSRA
CSRB
BIT 7
BIT 6
BIT 5
RECEIVER CLOCK SELECT
See Text
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TRANSMITTER CLOCK SELECT
See Text
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CRA
CRB
MISCELLANEOUS COMMANDS
See Text and Timing Requirement
DISABLE Tx
0 = No
1 = Yes
ENABLE Tx
0 = No
1 = Yes
DISABLE Rx
0 = No
1 = Yes
ENABLE Rx
0 = No
1 = Yes
NOTE: Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.
1998 Sep 04
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SCC2692.PDF ] | |
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