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PDF IDT71V65903 Data sheet ( Hoja de datos )

Número de pieza IDT71V65903
Descripción 256K x 36 / 512K x 18 3.3V Synchronous ZBT SRAMs
Fabricantes Integrated 
Logotipo Integrated Logotipo



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No Preview Available ! IDT71V65903 Hoja de datos, Descripción, Manual

256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs
IDT71V65703
IDT71V65903
Features
x 256K x 36, 512K x 18 memory configurations
x Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
x ZBTTM Feature - No dead cycles between write and read
cycles
x Internally synchronized output buffer enable eliminates the
need to control OE
x Single R/W (READ/WRITE) control pin
x 4-word burst capability (Interleaved or linear)
x Individual byte write (BW1 - BW4) control (May tie active)
x Three chip enables for simple depth expansion
x 3.3V power supply (±5%)
x 3.3V (±5%) I/O Supply (VDDQ)
x Power down controlled by ZZ input
x Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
Description
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBTTM, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle the associated data cycle occurs, be it
read or write.
The IDT71V65703/5903 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903
tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen
CEN is high and the internal device registers will hold their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71V65703/5903 have an on-chip burst counter. In the burst
mode, the IDT71V65703/5903 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V65703/5903 SRAMs utilize IDT’s latest high-performance
CMOSprocessandarepackagedinaJEDECStandard14mmx20mm100-
pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).
Pin Description Summary
A0-A 18
CE1, CE 2, CE2
OE
R/W
CEN
BW1, BW2, BW3, BW4
CLK
ADV/LD
LBO
ZZ
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
VSS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance Burst Address/Load New Address
Linear/Interleaved Burst Order
Sleep Mode
Data Input/Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/ O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Asynchronous
Synchronous
Static
Static
5298 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
©2002 Integrated Device Technology, Inc.
1
DECEMBER 2002
DSC-5298/03

1 page




IDT71V65903 pdf
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature(1)
VSS
VDD
VDDQ
Commercial
0°C to +70°C
0V 3.3V±5% 3.3V±5%
Industrial
-40°C to +85°C 0V 3.3V±5% 3.3V±5%
NOTES:
1. TA is the “instant on” case temperature.
5298 tbl 05
Pin Configuration — 256K x 36
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VSS(1)
VDD
VDD(2)
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VSS(1)
VDD
ZZ
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
5298 drw 02
,
Top View
100 TQFP
NOTES:
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. Pins 84 is reserved for a future 16M.
4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins TMS, TDI, TDO and TCK. The
current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.452

5 Page





IDT71V65903 arduino
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2)
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
Address
A0
X
A1
X
X
A2
X
X
A3
X
A4
X
X
A5
A6
A7
X
A8
X
A9
R/W ADV/LD CE1(1) CEN BWx OE
HL
L LXX
X H XLXL
HL
LLXL
X L HLXL
X H XLXX
HL
L LXX
X H XLXL
X L HLXL
L L LLLX
X H XLLX
L L LLLX
X L HLXX
X H XLXX
L L LLLX
HL
L LXX
L L LLLL
X H XLLX
HL
L LXX
X H XLXL
L L LLLL
I/O Comments
D1 Load read
Q0 Burst read
Q0+1 Load read
Q1 Deselect or STOP
Z NOOP
Z Load read
Q2 Burst read
Q2+1 Deselect or STOP
Z Load write
D3 Burst write
D3+1 Load write
D4 Deselect or STOP
Z NOOP
Z Load write
D5 Load read
Q6 Load write
D7 Burst write
D7+1 Load read
Q8 Burst read
Q8+1 Load write
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
5298 tbl 12
6.1412

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