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Número de pieza SAA4960
Descripción Integrated PAL comb filter
Fabricantes Philips 
Logotipo Philips Logotipo



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INTEGRATED CIRCUITS
DATA SHEET
SAA4960
Integrated PAL comb filter
Preliminary specification
File under Integrated Circuits, IC02
1996 Oct 15

1 page




SAA4960 pdf
Philips Semiconductors
Integrated PAL comb filter
Preliminary specification
SAA4960
FUNCTIONAL DESCRIPTION
Functional requirements
The PAL comb filter processes the video standards PAL B,
G and H. PAL D and I signals can also be processed but
with the drawback of a slightly reduced bandwidth.
For SECAM and SVHS signals, the input signals can be
bypassed to the output without processing by selecting the
BYPASS-mode.
A sync separation circuit is incorporated to generate
control signals for the internal clock processing. With a
sync compression of up to 12 dB the sync separator works
properly (see Fig.4).
The IC is controlled via four pins:
1. BYP forces the IC into the BYPASS-mode (comb filter
function off)
2. SSYN defines whether the COMB-mode is entered
synchronously or not and defines the polarity of the
BYP pin
3. FSCSW selects the reference frequency fsc or 2 × fsc
4. LPFION enables the internal pre-filter.
It is possible to select the following modes of operation:
COMB-mode: Luminance and chrominance comb filter
function active if BYPASS-mode not active.
BYPASS-mode: Signal processing not active, all clocks
inactive, Cext (pin 10) is bypassed to CO (pin 12) and
Yext/CVBS (pin 17) is bypassed to YO (pin 14) and
CVBSO (pin 15). This mode is forced via BYP (pin 3).
If the stimulus of the mode is changed, the IC is following
the new mode after the stabilization time given in Table 1.
Table 1 Stabilization time after mode change
MODE CHANGE
COMB-mode to BYPASS-mode
BYPASS-mode to COMB-mode
MAXIMUM
STABILIZATION
TIME
1 line
1 field
The mode change from BYPASS to COMB depends on
SSYN (pin 6) and can be asynchronous or synchronous
related to the vertical pulse. The mode change from
COMB to BYPASS is always performed asynchronously.
Pin description
FSC (PIN 1)
Input for the reference frequency fsc (see note 2 of Chapter
“Characteristics”) or 2 × fsc. For SECAM standard signals
the best signal performance in BYPASS-mode is achieved
by switching the FSC input signal off externally.
BYP (PIN 3)
Input signal that controls the operation mode. A low-pass
filter is added to the input for suppression of subcarrier
frequencies. Thus applications are supported where the
operation mode (COMB or BYPASS) is controlled by the
DC-level of the FSC input signal at pin 1. For those
applications the BYP input can be externally connected to
FSC (pin 1).
Depending on SSYN (pin 6) the function of BYP can be
adapted to a certain application with respect to the polarity
of the logic level and with respect to the behaviour when
entering the COMB-mode.
Dependent on SSYN the BYP input can be either inverted
or non-inverted with the function as shown in Table 2:
Table 2 Bypass function
SSYN BYP
LOW LOW
LOW HIGH
HIGH LOW
HIGH HIGH
SELECTED MODE
COMB-mode
BYPASS-mode
BYPASS-mode
COMB-mode
Dependent on SSYN the behaviour when entering the
COMB-mode is different for the both selectable logic
polarities while the BYPASS-mode is always entered
asynchronously (immediately).
Table 3 Behaviour when entering the COMB-mode
SSYN
ENTERING COMB-MODE
LOW immediately if BYP = LOW
HIGH synchronized by vertical pulse if BYP = HIGH
The PLL and the clock processing are always stopped if
the selected level for BYPASS is applied to BYP
(independent of the vertical pulse).
1996 Oct 15
5

5 Page





SAA4960 arduino
Philips Semiconductors
Integrated PAL comb filter
Preliminary specification
SAA4960
SYMBOL
PARAMETER
CONDITIONS
Cext (pin 10)
V10 input voltage (AC coupled)
R10 input resistance
C10 input capacitance
Z10 source impedance
CO (pin 12)
V10/V12
BYPASS-mode: CO/Cext
COMB-mode: transfer function C-path see Fig.8
V12
∆V12
DC offset voltage related to input
DC jump when forcing into
BYPASS-mode
R12
RL
CL
V17/V12
output resistance
load resistance (to ground)
load capacitance (to ground)
suppression (comb depth)
FPN
fixed pattern noise for divided clock
frequencies referenced to 0.7 V (p-p)
αcr crosstalk suppression at vertical
transients no-colour colour
S/N signal-to-noise ratio (0.7 V/Veff noise)
αcr
V12(p-p)
crosstalk between different inputs
FSC residue in BYPASS-mode related
to 700 mV (p-p)
Gd differential gain
FSCSW (pin 13)
VIH HIGH level input voltage
VIL LOW level input voltage
C13 input capacitance
Ileak input leakage current
1.25 V
fsc ±0.3fsc; note 2
see Fig.5 and
note 3
283 × fH
(283 43) × fH
(283 + 35) × fH
0.75fsc
fsc
1.5fsc
2fsc
see Fig.3
unweighted;
fsc ±0.3fsc; note 2
0 to 5 MHz
MIN. TYP. MAX. UNIT
0 3 dB
500 700 1000 k
− − 10 pF
− − 1 k
1 0
400
0.3
0
100
10
+1 dB
+400
450
100
25
mV
mV
k
pF
26 30
dB
20 24
dB
20 24
dB
− − −30 dB
− − −50 dB
− − −37 dB
− − −30 dB
26 30
dB
56 72
dB
− −60 40 dB
− − −60 dB
0.95
2
VCC
V
0 0.8 V
− − 10 pF
− − 10 µA
1996 Oct 15
11

11 Page







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