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PDF SAA4956TJ Data sheet ( Hoja de datos )
| Número de pieza | SAA4956TJ | |
| Descripción | 2.9-Mbit field memory with noise reduction | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAA4956TJ
2.9-Mbit field memory with noise
reduction
Preliminary specification
File under Integrated Circuits, IC02
1998 Dec 08
1 page  
Philips Semiconductors
2.9-Mbit field memory with noise reduction
Preliminary specification
SAA4956TJ
5 BLOCK DIAGRAM
handbook, full pageDw0id(tVh0) to D11(Y7) IE
12
NREN SCL SDA
14 to 3 18
40 1
20
WE RSTW SWCK
17 16 15
DATA INPUT AND
WRITE MASK
BUFFER (×13)
I2C-BUS
INTERFACE
12 + 1
I2C-bus control
D0 internal
IE internal
IE
internal
SAA4956TJ
INPUT BUFFER
(×3)
3
SERIAL WRITE/READ2 CONTROLLER
NOISE
REDUCTION
12 + 1
DATA
MUX
12 D-field delay
DATA MUX
12 12
12 + 1
mini cache write/read2 control + cache transfer
SERIAL WRITE REGISTER
20-WORD (×13)
20 × (12 + 1)
PARALLEL WRITE REGISTER
20-WORD (×13)
20 × (12 + 1)
read2
control
WRITE REGISTER
MINI CACHE
12-WORD (×12)
READ2
READ
REGISTER REGISTER
MEMORY ARRAY
245760-WORD (×12)
write
control
load write
block
address
read2
acknowledge
write
acknowledge
D0
internal
IE
internal
WRITE ADDRESS
COUNTER
MEMORY
ARBITRATION
LOGIC
READ2 ADDRESS
COUNTER
REFRESH ADDRESS
COUNTER
READ ADDRESS
COUNTER
+3.3 V
VDD 19
VDD(P) 21
VDD(O) 22
100 nF
GND 2
OGND 39
20 × 12
PARALLEL READ2 REGISTER
20-WORD (×12)
20 × 12
SERIAL READ2 REGISTER
20-WORD (×12)
20 × 12
PARALLEL READ REGISTER
20-WORD (×12)
20 × 12
SERIAL READ REGISTER
20-WORD (×12)
OE
internal
refresh
clock
CLOCK
OSCILLATOR
12 12
DATA MUX
DATA OUTPUT
BUFFER (×12)
27 to 38
12
Q0(V0) to Q11(Y7)
mini cache read control
OE
internal
INPUT BUFFER
(×4)
3
23 24 25 26
OE RE RSTR SRCK
read
control
read
acknowledge
load read
block
address
SERIAL READ CONTROLLER
MGR687
Pin 21 (VDD(P)) should be connected to the supply voltage of the driving circuit that generates the input voltages. This could be, for instance, 5.0 V
instead of 3.3 V. Pins 19 and 22 (VDD and VDD(O)) require a 3.3 V supply.
Fig.1 Block diagram.
1998 Dec 08
5
5 Page 
Philips Semiconductors
2.9-Mbit field memory with noise reduction
Preliminary specification
SAA4956TJ
7.2 Noise reduction function
handbook, full pagewidth
I2C-bus control:
chroma_inverted
DPCMin
data input
D0(V0), D1(V1)
D2(U0), D3(U1)
4
REFORMATTER
new U/V
−
delta U/V
LOW-PASS
FILTER 1
I2C-bus control:
unfiltered
LF delta U/V
D-field delay
D0(V0), D1(V1)
D2(U0), D3(U1)
4
REFORMATTER
old U/V
data input
D11(Y7) to D4(Y0)
8
new Y
−
delta Y
−+
LOW-PASS
FILTER 1
I2C-bus control:
unfiltered
LF delta Y
D-field delay
D11(Y7) to D4(Y0)
8
old Y
−+
ABS/LIMITER
U/V
AVERAGE
HF
delta
U/V
ABS/LIMITER
HF
delta
Y
LOW-PASS
FILTER 2
I2C-bus control:
Cadapt_gain
×
I2C-bus control:
chromafix and
Klumatochroma
Kchroma
Kchromafix
Kluma
LUT
×
+
LOW-PASS
FILTER 2
I2C-bus control:
Yadapt_gain
×
I2C-bus control:
lumafix
Klumafix
Kluma
LUT
×
+
Switch position is off.
I2C-bus control:
noise_shape
+
processed U/V
NOISE SHAPE
I2C-bus control:
DPCMout
FORMATTER
4
D to memory
D0(V0), D1(V1)
D2(U0), D3(U1)
I2C-bus control:
noise_shape
+
processed Y
NOISE SHAPE
8
D to memory
D11(Y7) to D4(Y0)
MGR689
Fig.3 Block diagram of noise reduction.
1998 Dec 08
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA4956TJ.PDF ] | |
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