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PDF SAA4951 Data sheet ( Hoja de datos )
| Número de pieza | SAA4951 | |
| Descripción | Memory controller | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA4951
Memory controller
Preliminary specification
File under Integrated Circuits, IC02
April 1994
1 page  
Philips Semiconductors
Memory controller
Preliminary specification
SAA4951
SYMBOL
VDD
HDFL
VDFL
VACQ
TEST
RSTW2
RSTW1
LLD
VSS
Note
1. I = Input
O = Output
PIN TYPE(1)
DESCRIPTION
36 −
positive supply voltage
37 O
horizontal synchronization signal, deflection part
38 O
vertical synchronization signal, deflection part
39 I
vertical synchronization signal, acquisition part
40 I
test input
41 O
reset write signal, memory 2
42 O
reset write signal, memory 1
43 I
line-locked clock signal, display part
44 −
ground
handbook, full pagewidth
IE1 7
WE1 8
STROBE 9
VDD 10
HRA/BLNA 11
VSS 12
LLA 13
IE2 14
WE2 15
CLV 16
ALDUV/VB 17
SAA4951WP
Fig.2 Pin configuration.
39 VACQ
38 VDFL
37 HDFL
36 VDD
35 HRDFL
34 VSS
33 LLDFL
32 P7
31 P6
30 P5
29 P4
MGH129
April 1994
5
5 Page 
Philips Semiconductors
Memory controller
Preliminary specification
SAA4951
Table 3 Mode registers.
REGISTER BIT
MODE0 0 (LSB)
1
2
3
MODE0
4
5
6
7 (MSB)
NAME
FSA0
FSA1
FSD0
FSD1
FORMAT0
FORMAT1
HDEL0
HDEL1
REMARKS
frequency select acquisition bit 0
frequency select acquisition bit 1
frequency select display bit 0
frequency select display bit 1
FSA1
FSA0
acquisition frequency
0 0 12.0 MHz
0 1 13.5 MHz
1 0 16.0 MHz
1 1 18.0 MHz
FSD1
FSD0
display frequency
0 0 27.0 MHz
0 1 27.0 MHz
1 0 32.0 MHz
1 1 36.0 MHz
control bit 0 for data format
control bit 1 for data format
FORMAT1
FORMAT0
Y:U:V data rate
0 0 4: 1: 1
0 1 4: 2: 2
1 0 4: 4: 4
1 1 4: 4: 4
horizontal delay control bit 0
horizontal delay control bit 1
the bits HDEL0, HDEL1 control the position of the internal vertical read enable
signals for RE1
HDEL1 HDEL0
0 0 2 lines earlier
0 1 1 line earlier
1 0 normal
1 1 1 line later
April 1994
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet SAA4951.PDF ] | |
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