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PDF SAA4945H Data sheet ( Hoja de datos )

Número de pieza SAA4945H
Descripción LIne MEmory noise Reduction IC LIMERIC
Fabricantes Philips 
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No Preview Available ! SAA4945H Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
SAA4945H
LIne MEmory noise Reduction IC
(LIMERIC)
Preliminary specification
File under Integrated Circuits, IC02
1997 Jun 10

1 page




SAA4945H pdf
Philips Semiconductors
LIne MEmory noise Reduction IC
(LIMERIC)
Preliminary specification
SAA4945H
SYMBOL
YO3
YO4
YO5
YO6
PIN TYPE
41 output
42 output
43 output
44 output
luminance output bit 3
luminance output bit 4
luminance output bit 5
luminance output bit 6
DESCRIPTION
handbook, full pagewidth
YO7 1
SNDA 2
SNCL 3
VRST 4
VDD1 5
GND1 6
YI7 7
YI6 8
YI5 9
YI4 10
YI3 11
SAA4945H
33 n.c.
32 GND6
31 WEO
30 VDD3
29 VDD2
28 GND5
27 GND4
26 TST0
25 TST1
24 TST2
23 GND3
MGK169
1997 Jun 10
Fig.2 Pin configuration.
5

5 Page





SAA4945H arduino
Philips Semiconductors
LIne MEmory noise Reduction IC
(LIMERIC)
Preliminary specification
SAA4945H
Output signals
YO0 TO YO7 (PINS 38 TO 44 AND 1)
8-bit wide digital luminance output bus
Data format: unsigned, dynamic range between
0 and 255.
UO1 AND UO0 (PINS 37 AND 36)
Colour difference signal U
Data format: 2’s complement, dynamic range between
128 and +127
Y : U : V format 4 : 1 : 1; see Table 8.
VO1 AND VO0 (PINS 35 AND 34)
Colour difference signal V
Data format: 2’s complement, dynamic range between
128 and +127
Y : U : V format 4 : 1 : 1; see Table 8.
WEO (PIN 31)
Write enable output
Write enable indicates the time when active samples (Y,
U and V) are present
Timing relation (see Fig.6) depending on write enable
select signal (WES) in status register; to adapt to
different external video memories
The number of output samples is a multiple of 4
The write enable output sequence is a copy of the write
enable input sequence of the previous line (see Fig.6)
with a shift of one line
The last line in field is not processed.
handbook, full pagewidth
Va
VRST
WEI L(n1)
tVa(min)H
tsu(Va)
t(WE-VRST)LH
L(n)
t(Va-WE)LH
t(Va-VRST)LH
L(0) L(1) L(2)
WEO
L(n2)
L(n1)
internal flag
to mask
WEO
1 clk cycle
Fig.6 Timing diagram for WEO blanking and Va.
L(0) L(1)
MGK174
1997 Jun 10
11

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