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PDF SAA3500H Data sheet ( Hoja de datos )
| Número de pieza | SAA3500H | |
| Descripción | Digital audio broadcast channel decoder | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAA3500H
Digital audio broadcast channel
decoder
Preliminary specification
File under Integrated Circuits, IC01
2000 Jun 14
1 page  
Philips Semiconductors
Digital audio broadcast channel decoder
Preliminary specification
SAA3500H
7 PINNING
SYMBOL PIN TYPE
DESCRIPTION
ADC
1 input analog-to-digital converter DC input
AIF 2 input analog-to-digital converter IF input
VSSA
ADE
3 ground analog supply ground
99 input analog-to-digital converter enable (active LOW)
VDDA
INP[0:9]
100 supply analog voltage supply (+3.3 V)
8 to 17 input 2048 kHz IF or baseband digital parallel input data (8 or 10 bits)
ADCLK
19 output analog-to-digital clock output 8192 kHz if BYP = HIGH, 4096 kHz if BYP = LOW
IQS 20 input clock signal indicating I or Q baseband data if BYP = LOW;
signal for swapping I and Q data bytes if BYP = HIGH
BYP
21 input IF input stage bypass (active LOW)
FSI 22 input frame sync input (LOW indicates DAB null symbol detection)
FSO
23 output null detector/frame sync output (LOW indicates DAB null symbol position)
SLI 24 output AGC synchronization lock indicator (HIGH if synchronized)
AGC
25 output AGC level comparator output (HIGH if input sample > reference level, else LOW)
OSCI
4 input oscillator or system clock input, 24576 kHz
OSCO
5 output oscillator output
MCLK
41 output master clock output, 24576 kHz
VSS 7, 18, supply digital supply ground
26, 40,
60, 80
and 94
VDD 6, 28, supply digital voltage supply (+3.3 V)
42 and
79
TEST
92 input connect to ground for proper operation
OUT[0:7] 32 to 39 output baseband or channel impulse response output
OCLK
27 output output data clock (negative edge indicates new data)
OIQ 29 output output I or Q select signal if OCIR = HIGH, or frame trigger if OCIR = LOW
OCIR
30 input output select: baseband if OCIR = HIGH, CIR if OCIR = LOW
OEN
31 input output enable (active LOW)
CFIC
51 output microcontroller interface signal indicating Fast Information Channel (FIC) processing
CMODE
CDATA
CCLK
52 input microcontroller interface mode input (only L3-bus)
53 I/O
microcontroller interface serial data I2C-bus or L3-bus (5 V tolerant)
54 input microcontroller interface clock input I2C-bus or L3-bus
RESET
55 input chip reset input (active LOW)
A[17:11] 62 to 68 output address outputs external RAM
A[10:0] 81 to 91 output address outputs external RAM
WR 61 output write data to RAM (active LOW)
RD 69 output read data from RAM (active LOW)
A17 70 output address bit 17 inverted for second RAM (128k × 8)
D[0:7]
71 to 78 I/O data input/output external RAM
2000 Jun 14
5
5 Page 
Philips Semiconductors
Digital audio broadcast channel decoder
Preliminary specification
SAA3500H
In the CIR output mode the channel impulse response is clocked out in a burst of N (unsigned) samples at 64 kHz each
frame after CIR processing (bit SyncBusy = logic 0). The edges of the frame trigger signal (OIQ) allow to trigger a CIR
display either at the start of the symbol or at the start of the symbol guard. In the latter case the CIR peak for a Gaussian
channel will be at the left of the display.
9.4 Serial output interface
The serial output interface is intended for transferring up to three sub-channels to the source decoder(s) with a total
maximum bit rate of 384 kbit/s. The sub-channels for these outputs should be selected with the appropriate I2C or L3
commands. The output clock is 384 kHz. Each sub-channel has its own serial data and data valid line, but the clock is
common. Serial output data shall be latched on the rising edge of SOC.
SOC
SOD
SOV
Fig.8 DAB3 serial output.
9.5 Simple full capacity output
This interface provides serial access to all the Viterbi decoder output bits without any formatting. Transmission framing
is indicated by the CFIC window, which can also be used to separate the FIC data (CFIC = HIGH) from the Main Service
Channel (MSC) data (CFIC = LOW). The bit CFICMode can be used to signal on CFIC the beginning of the selected
sub-channels (CFICMode = logic 0). The clock is a 3072 kHz burst clock, activated for each new output bit.
Accompanied with the data is the error flag, obtained by re-encoding the Viterbi output bits and comparison with the
corresponding Viterbi decoder input bits (REF = HIGH for error bit).
CFIC
RDC
SFCO
REF
CFICMode = 0
Fig.9 Simple full capacity output (CFICMode = logic 1).
9.6 RDI output
For external use a bi-phase modulated output (RDO) is provided, which carries all the FIC and MSC data, formatted
according to the DAB receiver data interface specification “EN 50255”, which is based on the IEC 60958 digital audio
interface. Optionally, a clock (6144 kHz) and word select signal (48 kHz) can be provided (instead of SFCO signals).
Transmitter Identification Information (TII) is not signalled on this RDI. The FIC however is always signalled, with the
Cyclic Redundancy Check (CRC) performed and the Error Check Field containing the resulting CRC (normally 0).
Selected sub-channels will be directed to the RDI interface in the extended capacity mode (22 bits for MSC), but the
number of RDI frames and the reliability are not signalled (i.e., set to all logic 0s and all logic 1s, respectively).
2000 Jun 14
11
11 Page | ||
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| PDF Descargar | [ Datasheet SAA3500H.PDF ] | |
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