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Número de pieza SAA3323H
Descripción Drive processor for DCC systems
Fabricantes Philips 
Logotipo Philips Logotipo



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INTEGRATED CIRCUITS
DATA SHEET
SAA3323
Drive processor for DCC systems
Preliminary specification
File under Integrated Circuits, IC01
May 1994
Philips Semiconductors

1 page




SAA3323H pdf
Philips Semiconductors
Drive processor for DCC systems
Preliminary specification
SAA3323
SYMBOL
A4
VSS3
VDD3
A5
A6
A7
A12/PINO5
A14/PINO1
A16/PINO3
A15/PINO4
WEN
A13/PINO2
A8
VDD4
VSS4
A9/CAS
A11
SPEED
PINO2
WDATA
TCLOCK
VSS5
VDD5
TEST2
RDMUX
Vref(p)
Vref(n)
SUBSTR
BIAS
VSSA
VDDA
ANAEYE
RDSYNC
VDD6
VSS6
CHTST1
CHTST2
TEST0
TEST1
PIN
QFP80 TQFP80
DESCRIPTION
TYPE(1)
39 37 address SRAM; address DRAM
O (2 mA)
40 38 digital ground
S
41 39 digital supply voltage
S
42 40 address SRAM; address DRAM
O (2 mA)
43 41 address SRAM; address DRAM
O (2 mA)
44 42 address SRAM; address DRAM
O (2 mA)
45 43 address SRAM; Port expander output 5
O (2 mA)
46 44 address SRAM; Port expander output 1
O (2 mA)
47 45 address SRAM; Port expander output 3
O (2 mA)
48 46 address SRAM; Port expander output 4
O (2 mA)
49 47 write enable for RAM
O (2 mA)
50 48 address SRAM; Port expander output 2
O (2 mA)
51 49 address SRAM; address DRAM
O (2 mA)
52 50 digital supply voltage
S
53 51 digital ground
S
54 52 address SRAM; CAS for DRAM
O (2 mA)
55 53 address SRAM
O (2 mA)
56 54 Pulse Width Modulation (PWM) capstan control output for deck Ot (1 mA)
57 55 Port expander output 2
Ot (1 mA)
58 56 serial output to write amplifier
O (1 mA)
59 57 3.072 MHz clock output for tape I/O
O (1 mA)
60 58 digital ground
S
61 59 digital supply voltage
S
62 60 TEST mode select; do not connect
63 61 analog multiplexed input from read amplifier
64 62 ADC positive reference voltage
65 63 ADC negative reference voltage
66 64 substrate connection
67 65 bias current for ADC
68 66 analog ground
Ipd
IA
IA
IA
IA
IA
S
69 67 analog supply voltage
S
70 68 analog eye pattern output
71 69 synchronization output for read amplifier
OA
O (1 mA)
72 70 digital supply voltage
S
73 71 digital ground
S
74 72 channel test pin 1
O (1 mA)
75 73 channel test pin 2
O (1 mA)
76 74 TEST mode select; do not connect
77 75 TEST mode select; do not connect
Ipd
Ipd
May 1994
5

5 Page





SAA3323H arduino
Philips Semiconductors
Drive processor for DCC systems
Preliminary specification
SAA3323
Table 7 Digital equalizer register names.
REGISTER NAME
CMD
STATUS0
STATUS1
COEFCNT
FCTRL
CHT1SEL
CHT2SEL
ANAEYE
AEC
SSPD
INTMASK
DEQ2SET
CLKSET
READ/WRITE
W
R
R
W
W
W
W
W
R/W
R
W
W
W
DATA STREAMS
The digital equalizer module has one write only and one
read only data stream that are accessible via the
L3 interface and they are shown in Table 8.
Table 8 Digital equalizer data streams.
DATA STREAM NAME
FIR coefficients to buffer bank
FIR coefficients from active bank
READ/WRITE
W
W
DIGITAL EQUALIZER COMMANDS
These are the commands that need to be sent to the digital
equalizer in order to access the indirectly accessible
registers and the data streams.
Table 9 Digital equalizer commands.
NAME
WRCOEF
RDCOEF
LDCOEFCNT
LDFCTRL
LDT1SEL
LDT2SEL
LDTAEYE
LDAEC
RDAEC
RDSSPD
LDINTMSK
LDDEQ3SET
LDCLKSET
COMMAND BYTE
76543210
EXPLANATION
0 0 1 1 0 0 0 0 write FIR coefficients to the digital equalizer buffer bank
0 0 1 0 0 0 0 0 read FIR coefficients from the digital equalizer active bank
0 0 0 1 0 0 1 1 load FIR coefficient counter
0 0 0 1 0 1 0 0 load filter control register
0 0 0 1 0 1 1 0 load CHTST1 pin selection register
0 0 0 1 0 1 1 1 load CHTST2 pin selection register
0 0 0 1 1 0 0 0 load ANAEYE channel selection register
0 0 0 1 1 0 0 1 load AEC counter
0 0 1 0 0 0 1 0 read AEC counter
0 0 1 0 0 1 0 0 read SEARCH speed register
0 0 0 1 0 0 1 0 load interrupt mask register
0 0 0 1 0 0 0 0 load digital equalizer settings register
0 0 0 1 0 0 0 1 load PLL clock extraction settings register
Table 10 Filter control register.
BIT
Meaning
Default
765432 1 0
µCS(1)
SH1
SH0
Reserved
000010 1 1
Note
1. µCS is a microcontroller controlled coefficient bank switch. This causes the filter coefficients to be activated at a time
that is safe for the digital equalizer, i.e. at the end of the FIR program and that the complete value of coefficient
number 9 has been received.
May 1994
11

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