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PDF SAA2503 Data sheet ( Hoja de datos )
| Número de pieza | SAA2503 | |
| Descripción | MPEG2 audio decoder | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA2503
MPEG2 audio decoder
Objective specification
File under Integrated Circuits, IC01
1997 Jul 02
1 page  
Philips Semiconductors
MPEG2 audio decoder
Objective specification
SAA2503
SYMBOL
VCCP
EXTAL
SCL
GNDS1
SDA
RESET
MODA
MODB
MODC
VCCS1
HA0
HA2
HREQ
GNDS2
SDO2
SDO1
SDO0
VCCS2
SCKT
WST
SCKR
GNDQ3
VCCQ3
GNDS3
WSR
SDI1
SDI0
DSO
DSI/OS0
DSCK/OS1
n.c.
n.c.
n.c.
n.c.
DR
SDB
MUTE
GNDD1
BUSY
I2CEN
VCCD1
1997 Jul 02
PIN I/O
DESCRIPTION
41 supply supply voltage for the Phase Locked Loop (PLL)
42 I external clock/crystal Input
43 I I2C-bus serial clock
44 GND isolated ground 1 for the SHI I/O drivers
45 I/O I2C-bus data and acknowledge
46 I hardware reset for the microcontroller
47 I mode select A
48 I mode select B
49 I mode select C
50 supply isolated power supply 1 for the SHI I/O drivers
51 I/O I2C-bus slave address 0
52 I I2C-bus slave address 2
53 I host request
54 GND isolated ground 2 for the SHI I/O drivers
55 O not used
56 O not used
57 O serial data output 0
58 supply isolated power supply 2 for the SHI I/O drivers
59 O transmit serial clock
60 O transmit word select
61 I receive serial clock
62 GND ground 3 dedicated for the PLL
63 supply isolated power supply 3 for some sections of the internal chip logic
64 GND isolated ground 3 for the SHI I/O drivers
65 I receive word select
66 I serial data input 1
67 I not used
68 O not used
69 O not used
70 O not used
71 − not connected
72 − not connected
73 − not connected
74 − not connected
75 I not used
76 I/O general purpose I/O
77 I/O general purpose I/O
78 GND ground 1 for some sections of internal logic
79 I/O general purpose I/O
80 I/O general purpose I/O
81 supply isolated power supply 1 for some sections of the internal chip logic
5
5 Page 
Philips Semiconductors
MPEG2 audio decoder
Objective specification
SAA2503
AUDIO OUTPUTS INTERFACING
Also see Chapter “Interfacing to the A/V splitter”.
Stereo output for DAC
The output stereo down-mixing signal is in I2S-bus format
and can be directly connected to a DAC. The SDO0
(pin 57) provides the output for the serial audio data.
Furthermore, SCKT (pin 59) provides the I2S-bus clock
and WST (pin 60), the I2S-bus word select.
IEC 958 transmitter
The format of the IEC 958 interface consists of a sequence
of IEC 958 sub frames. Each IEC 958 sub frame is
normally used to carry one LPCM sample. The IEC 958
sub frame may also be used to convey data words.
The non-PCM encoded audio bitstreams to be transferred
are formed into data bursts. These bitstreams consist of a
sequence of data words.
Each data burst contains a 64-bit burst_preamble,
followed by the burst_payload.
The burst_preamble provides a sync_word, information on
the burst_payload and the bitstream number.
The interface may convey one or more bitstreams. Each
type of bitstream may impose a particular requirement for
the repetition time for the data bursts that make up the
bitstream.
The 16-bit data words of a data burst are placed in time
slots 12 to 27 of an IEC 958 sub frame. In the consumer
application, both odd and even IEC 958-sub frames (CH1
and CH2) are simultaneously used to carry 32-bit data
words (32-bit mode). This allows the consumer IEC 958 to
convey either 2-channel LPCM audio, or a set of
alternating data words, but not both simultaneously.
For more information see IEC 1937.
The IEC 958 interface is of the digital audio interface. This
conveys LPCM or encoded audio bitstreams according to
IEC 1937 (IEC 1937), using the ‘network layer’ of IEC 958
(IEC 958). The audio data will be accompanied by a
validity bit, channel status and user data (sub code).
Table 3 Pinning of IEC 958 interface
ADO
ACI
PINS
DESCRIPTION
Audio Data Output
Audio Clock Input; note 1
Note
1. The ACI clock is 256fs (or 512 or 384fs).
PIN NUMBER
DIRECTION
30 output
31 input
INTERFACING WITH THE MICROCONTROLLER
Flags
The SAA2503 has 3 flags which, after a hardware reset,
are all initialized to logic 1.
1. I2C-bus communication disabled (pin 80); I2CEN: this
flag is set to logic 0 when the SAA2503 is ready to
accept messages via the I2C-bus.
2. Life test (pin 79); BUSY: when the SAA2503 operates
in the MPEG decoding mode, this flag toggles
whenever the SAA2503 has detected a
synchronization pattern. The flag will then produce a
20.833 Hz (fas = 48 kHz) and a 19.140 Hz
(fas = 44.1 kHz) signal. It can be used to monitor the
MPEG decoding process. When this flag no longer
toggles there is an error. When the SAA2503 operates
in one of the LPCM modes however, the flag produces
either a 23.437 Hz (fas = 48 kHz) or a 21.533 Hz
(fas = 44.1 kHz) signal.
3. MPEG decoding active and synchronised (pin 77);
MUTE: when the SAA2503 operates in the MPEG
decoding mode, this flag indicates the state of the
SAA2503 (synchronized or not). When this pin is at
logic 1 the SAA2503 is out of sync, when set to logic 0
the SAA2503 is synchronized. It will not change state
when the SAA2503 remains synchronized. When the
SAA2503 is operating in one of the LPCM modes, the
MUTE pin is set at logic 1 during initialization and
logic 0 during processing.
I2C-bus interface
The I2C-bus interface supports data rates of up to
400 kbits/s. For a description of the I2C-bus see
“The I2C-bus and how to use it”, ordering number
9398 393 40011.
For a description of the I2C-bus commands controlling the
SAA2503 see Table 1.
1997 Jul 02
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet SAA2503.PDF ] | |
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