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PDF SAA1305T Data sheet ( Hoja de datos )
| Número de pieza | SAA1305T | |
| Descripción | On/off logic IC | |
| Fabricantes | Panasonic Semiconductor | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA1305T
On/off logic IC
Product specification
Supersedes data of 1998 Sep 04
2004 Jan 15
1 page  
Philips Semiconductors
On/off logic IC
Product specification
SAA1305T
handbook, halfpage
D0 1
24 CHI
D1 2
23 RP
D2 3
22 LED
D3 4
21 VDD
D4 5
D5 6
D6 7
20 SCL
19 VSS
SAA1305T
18 SDA
D7 8
17 XTAL2
ON/OFF 9
16 XTAL1
RES 10
15 OSC2
WD 11
14 OSC1
TS 12
13 TST
MGR201
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Figure 1 shows the block diagram for the SAA1305T.
Details are explained in the subsequent sections.
Watch and alarm functions
An internal RAM (watch register) counts automatically the
seconds for one-day (one-day reset also automatically).
The watch register can be set and read from the I2C-bus.
An alarm function is possible via a second RAM (alarm
register) and is programmable via the I2C-bus. The alarm
timer triggers pin CHI and if enabled the reset pulse on
pin RP. After a device reset the content of the alarm
register is FFFFH (alarm function is disabled) and the
content of watch register is 0000H.
LED control
The I2C-bus interface control (see Table 10) for the LED
contains:
• Two function control bits
• Two control bits for the blink LED frequency
• Two control bits for the blink LED duration time.
All bits are combined within the LED register.
Reset time
The pulse time on pin RP is selectable via an I2C-bus
command; see Table 8. The default value after Power-on
reset is the longest time (20 ms). Selectable pulse times
via the control register are: 1, 5, 10 and 20 ms.
With the rising edge of the reset pulse all inputs, except the
Watchdog timer and VL timer, are disabled until the
I2C-bus command ENABLE-RESET. Each pulse on
pin RP resets the internal I2C-bus interface.
On/off
The output signal on pin ON/OFF remains HIGH after a
trigger event. Trigger sources are:
• Alterations on any of the inputs D0 to D7
• An impedance detection
• A device reset
• A VL (is an undervoltage) timer or alarm timer event
• An oscillator fault.
In the event of a five time failed Watchdog timer trigger or
missed I2C-bus read sequence (after a change information
indication), an internal logic circuit will reset pin ON/OFF
and set the IC in the standby mode. It is also possible to
control pin ON/OFF during the run mode via an I2C-bus
command (see Table 8, bit 1). In principal two stable IC
modes are possible; see Fig.3:
1. Standby mode: an oscillator fault and the following IC
function groups can trigger a reset pulse to enter the
run mode;
a) Watch (alarm timer).
b) Supply (device reset).
c) Inputs D0 to D7 (a change on any of these inputs
or an impedance detection).
The Watchdog timer and the VL timer are disabled in
the standby mode.
2. Run mode: only the Watchdog timer (WD), an
oscillator fault, a missed I2 C-bus communication and
the reset input (RES) can trigger a reset pulse. It is
possible to enter the standby mode via control register
bit 0; see Table 8.
The dynamic mode or wait mode is possible but can only
be started from the run mode (see Section “VL timer”).
2004 Jan 15
5
5 Page 
Philips Semiconductors
On/off logic IC
Product specification
SAA1305T
I2C-BUS INTERFACE COMMANDS
I2C-bus communication is only possible in the run mode.
Read mode operations
Only the sequential read mode is possible. The IC starts
after every device select (code 48) to output data 1.
However, in this event the master does acknowledge the
data output and the IC continues to output the next data in
sequence; see Figs 6 and 7.
To terminate the stream of bytes, the master must not
acknowledge the last byte output, but must generate a
STOP condition. The output data is from consecutive byte
addresses, with the internal byte address counter
automatically incremented after each byte output. In the
event of higher read sequences than available data bytes,
the 7th and 8th bit content are 0 and the address counter
will generate a wrap around (output at address 0).
The definitions of the bits are given in Tables 5, 6 and 7.
handbook, full pagewidth
acknowledge
acknowledge
S DEVICE SELECT
DATA 1
START
condition
R/W
acknowledge
no acknowledge
DATA N
P
STOP
condition
MGR221
Fig.6 I2C-bus read mode sequence.
handbook, full pagewidth
START DEVICE SELECT
byte
STATUS
0
OLD NEW WATCH STOP
1 2 3, 4, 5, 6, 7
MGR222
2004 Jan 15
Fig.7 I2C-bus read data sequence.
11
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