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PDF SA9205 Data sheet ( Hoja de datos )

Número de pieza SA9205
Descripción 6/3 X 8 PORT EXPANDER
Fabricantes Sames 
Logotipo Sames Logotipo



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sames
SA9203/5
6/3 X 8 PORT EXPANDER
FEATURES
n Six (SA9203) or three (SA9205) 8-Bit n Readback of all control and port
I/O Ports
registers
n Each bit of one port independently n Interfaces directly with multiplexed
programmable as input or output
address and data bus microprocessors/
n Five (SA9203) or two (SA9205)
microcontrollers
remaining ports can be individually n Internal address latch
configured as input or output. (Direction n Single +5V power supply
applicable to all 8 pins of each port.)
n Low power CMOS
n One 8-Bit port programmable as either
atched or transparent inputs
n Completely static operation
n Supports byte-wide and bit-wide I/O n TTL-level compatibility
port addressing modes on all ports
DESCRIPTION
The SAMES SA9203/5 Port Expander is a
CMOS device suited to microprocessor
based applications requiring input/output
port expansion. The device interfaces very
simply to any microcontroller/micro-
processor with a multiplexed address/data
bus structure.
The SA9203 includes 8 independently
programmable I/O pins for Port A and Port
B to F (5 ports) independently programmable
as I/O. It is packaged in a PCB efficient 68
pin PLCC package. The SA9205 includes
8 independently programmable I/O pins for
Port A with Port B and Port C as indepen-
dently programmable I/O, packaged in a
cost effective 44 pin PLCC package.
FIGURE 1: PIN CONNECTION FOR
SA9203
PA 0 10
PA 1 11
PA 2 12
PA 3 13
PA 4 14
PA 5 15
PA 6 16
PA 7 17
VDD 18
PB0 19
PB 1 20
PB2 21
PB3 22
PB4 23
PB5 24
PB6 25
PB7 26
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
SA9203
60 PF 7
59 PF 6
58 PF 5
57 PF 4
56 PF 3
55 PF 2
54 PF 1
53 PF 0
52 V DD
51 PE 7
50 PE 6
49 PE 5
48 PE 4
47 PE 3
46 PE 2
45 PE 1
44 PE 0
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DR-01266
4491
PDS039-SA9203/5-001
REV. A
1/14
20-08-96

1 page




SA9205 pdf
SA9203/5
PIN DESCRIPTION for SA9203
Pin Type Designation
18,52
VDD
1,35 VSS
61..68 I/O AD0..AD7
2
3I
4I
5I
6I
N/C
CS
ALE
RD
WR
7O
INT
8I
RST
9I
STB
10..17 I/O PA0..PA7
19..26 I/O PB0..PB7
27..34
36..43
44..51
53..60
I/O
I/O
I/O
I/O
PC0..PC7
PD0..PD7
PE0..PE7
PF0..PF7
sames
Description
+5V Supply Input
0V ground Reference
3-state address/data lines that interface with the CPU
lower 8-bit address/data bus. The 8-bit address is
latched into the SA9203 internal address latch on the
falling edge of ALE. The 8-bit data is respectively
written into and read out of the SA9203 on WR and RD
signals.
Not connected.
Active low input signal used to select the device.
This control signal latches the address on the AD0..7
lines on the falling edge of ALE.
Input low on this line enables the data bus buffers.
Input low on this line causes the data on the address/
data bus to be written to the I/O ports and, control
registers.
If enabled via A.6, this output will be set (active edge
polarity programmed by D6 and output polarity
programmed via D7 of the Port B-F direction control
register) after data has been latched into PORT A.
Input low on this line resets the chip and all internal
registers and all ports to input mode (The register
contents after a reset pulse will be described later).
Input data on PORT A pins will be latched when STB is
active and transparent otherwise (polarity programmed
by D5 of the Port B-F direction control register)
8 general purpose I/O pins comprising PORT A. This
port supports individual input or latched output
configuration of each pin. In addition,each pin of PORT
A selected as an input can be programmed to be
latched or transparent.
8 general purpose I/O pins comprising PORT B. All 8
pins are programmed to be either latched outputs or
transparent inputs.
Identical to PORT B
Identical to PORT B
Identical to PORT B
Identical to PORT B
5/14

5 Page





SA9205 arduino
FIGURE 13: µP Write Waveforms
CS
AD0 -8/A 8
ALE
WR
DR-01271
ADDRESS
tAL t LA
tLL
t CLL
t LC
SA9203/5
DATA VALID
t DW tCL
t WD
t RV
t CC t WT
FIGURE 14: µP Strobe/Interrupt Waveforms
STB
OR*
STB
tSS t SI
INT
or
INT
tPSS tPHS
INPUT
DATA
FROM
PORTA
* DEPENDENT ON SP
# DEPENDENT ON IP
DR-01272
t RDI
sames
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