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PDF SA9110A Data sheet ( Hoja de datos )
| Número de pieza | SA9110A | |
| Descripción | MONOCHIP THREE PHASE BIDIRECTIONAL | |
| Fabricantes | Sames | |
| Logotipo |  |
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sames
SA9110A
MONOCHIP THREE PHASE BIDIRECTIONAL
KILOWATT HOUR METERING IC
FEATURES
n Performs bidirectional energy meter-
ing and directly drives a LCD with 7
digits plus announciators
n 4 externally selectable on-chip tariff
registers
n An additional total energy register
n Meets the IEC 521/1036 Specification
requirements for Class 1 AC Watt hour
meters
n Optical interface for electronic reading
according to IEC1107 Mode D
DESCRIPTION
The SAMES SA9110A Three Phase bidi-
rectional energy metering integrated cir-
cuit has an integrated Liquid Crystal Dis-
play (LCD) driver for a 7 digit (7 segment)
display as well as 4 multiple tariff registers.
The SA9110A performs the active power
calculation.
The method of calculation takes the power
factor into account.
The measured energy is displayed in kilo
Watt hours (kWh). The SA9110A is capa-
ble of driving a display having a resolution
of 1/10 kWh.
This innovative universal energy metering
integrated circuit is ideally suited for en-
ergy measurement in three phase sys-
tems.
The SA9110A integrated circuit is avail-
able in a 68 pin plastic leaded chip carrier
(PLCC-68) package type.
4365
n Pulse output for calibration
n Total power consumption rating below
40mW
n Adaptable to different types of current
sensors
n Operates over a wide temperature
range
n Precision voltage reference on-chip
n Protected against ESD
PIN CONNECTIONS
TP61 61
SDO 62
PCLK 63
PDTA 64
PGM 65
PB 66
SR[0] 67
SR[1] 68
VDD 1
VSS 2
VREF 3
CON3 4
COP3 5
IVP3 6
IVP2 7
IVP1 8
TP9 9
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
43 COFF
42 R[3]
41 R[2]
40 R[1]
39 R[0]
38 VBA
37 V SS
36 CINP
35 CIPP
34 CONP
33 COPP
32 IIP3
31 IIN3
30 IIP2
29 IIN2
28 IIP1
27 IIN1
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
DR-00952
Package: PLCC-68
PDS039-SA9110A-001 REV. B
1/18
28-08-1996
1 page  
SA9110A
PIN DESCRIPTION (continued)
Pin Designation Type
16 CON1
Analog
17 COP1
Analog
15 CON2
Analog
14 COP2
Analog
4 CON3
Analog
5 COP3
Analog
34 CONP
Analog
33 COPP
Analog
19 CIN1
Analog
18 CIP1
Analog
21 CIN2
Analog
20 CIP2
Analog
23 CIN3
Analog
22 CIP3
Analog
36 CINP
Analog
35 CIPP
Analog
3 VREF
Analog
62
SDO
Open drain
67 SR[0]
Input
68 SR[1]
Input
66 PB
Input
65 PGM
Input
64 PDTA
63 PCLK
9 TP9
10 TP10
11 TP11
13 TP13
24 TP24
26 TP26
44 TP44
61 TP61
Input
Input
Description
Connections for outer loop capacitors of A/D
converters
Connections for inner loop capacitors of A/D
converters
Connection for reference current setting resistor
Pulse rate output. Serial data output when PB is low
Control for tariff register selection (on-chip pull-up)
Control for tariff register selection (on-chip pull-up)
Push Button: Display select/start serial data
transmission on SDO (on-chip pull-up)
Programming Mode . It is recommended that pin PGM
be connected to VDD via a 470Ω resistor to guard
against transients or noise.
Programming Data (on-chip pull-down)
Programming Clock
Manufacturer's test pins (Leave unconnected)
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5/18
5 Page 
SA9110A
Word Bit Function
number number
5 27..0 Register 'Total'
6 31..16 ROM
6 15..0 Manufacturers
Identification
7 31..28 ROM
7 27..0 System
Identification
8 31..0 ROM
9 31 Programmed slope
select
9 30..25 ROM
9 24-22 SAMES defined
register
9 21 Sign of offset
9 20..14 Offset
9 13 Sign of slope
9 12..0 Slope
10 31..0 ROM
Description
Registers 1, 2, 3 and 4 are added and stored in the
register 'Total'
Don't care
16 bits are available for the manufacturer of the
metering system as a system identification
Don't care
28 bits are available for the manufacturer of the
metering system as a system identification
Don't care
Programmed slope select bit must be set if the
default slope in ROM is not used
Don't care
Bits must be set to 0 for correct functionality
By setting the sign bit a negative value is indicated
Offset of the device in binary
By setting the sign bit a negative value is indicated
Slope of the device in binary. (default = 11389)
Don't care
The first bit of the programming data is written to word number 1, bit 31. The last
bit is written to word number 10, bit 0.
PGM
PCLK
PDTA
BIT-N0
WORD-NO
31 30 29 28 27 26 25 24 23
111111111
0
10
DR-00957
Programming procedure:
The PGM pin is pulled low and the PCLK pin should be clocked with an external
clock. The programming data on the PDTA pin must be stable during the rising edge
of the clock signal on PCLK.
The clock signal on PCLK should not exceed 200 kHz and does not have to be
synchronised with the oscillator frequency (FOSC).
Programming mode is interrupted if PGM goes high.
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11/18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SA9110A.PDF ] | |
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