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PDF SA8026 Data sheet ( Hoja de datos )
| Número de pieza | SA8026 | |
| Descripción | 2.5GHz low voltage fractional-N dual frequency synthesizer | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
SA8026
2.5GHz low voltage fractional-N
dual frequency synthesizer
Product specification
Supersedes data of 1999 Apr 16
1999 Nov 04
Philips
Semiconductors
1 page  
Philips Semiconductors
2.5GHz low voltage fractional-N dual frequency
synthesizer
Product specification
SA8026
CHARACTERISTICS
VDDCP = VDD = +3.0V, Tamb = +25°C; unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP.
Supply; pins 3, 13
VDD
VDDCP
IDDTotal
Digital supply voltage
Analog supply voltage
Synthesizer operational total supply current
VDDCP w VDD
VDD = +3.0V
(with main and aux on)
2.7 –
2.7 –
– 10
IStandby
Total supply current in power-down mode
RFin main divider input; pins 5, 6
logic levels 0 or VDD
–1
fVCO
VRFin(rms)
VCO input frequency
AC-coupled input signal level
Rin (external) = Rs = 50Ω;
single-ended drive;
max. limit is indicative
@ 500 to 2500 MHz
350
–18
–
–
ZIRFin
Input impedance (real part)
CIRFin
Typical pin input capacitance
Nmain
Main divider ratio
fPCmax
Maximum loop comparison frequency
AUX reference divider input; pin 12
fVCO = 2.4 GHz
fVCO = 2.4 GHz
indicative, not tested
– 300
–1
512 –
––
fAUXin
VAUXin
Input frequency range
AC-coupled input signal level
Rin (external) = RS = 50Ω;
max. limit is indicative
20
–18
80
–
–
–
ZAUXin
Input impedance (real part)
CAUXin
Typical pin input capacitance
NAUX
Auxiliary division ratio
Reference divider input; pins 15, 16
fVCO = 500 MHz
fVCO = 500 MHz
– 3.9
– 0.5
128 –
fREFin
VRFin
Input frequency range from TCXO
AC-coupled input signal level
single-ended drive;
max. limit is indicative
5–
360 –
ZREFin
Input impedance (real part)
CREFin
Typical pin input capacitance
RREF
Reference division ratio
Charge pump current setting resistor input; pin 14
fREF = 20 MHz
fREF = 20 MHz
SA = SM = ”000”
– 10
–1
4–
RSET
External resistor from pin to ground
6 7.5
VSET
Regulated voltage at pin
RSET = 7.5 kΩ
– 1.25
Charge pump outputs (including fractional compensation pump); pins 8, 9, 11; RSET = 7.5 kΩ, FC = 80
ICP Charge pump current ratio to ISET1
Current gain = IPH/ISET
–15
IMATCH
Sink-to-source current matching
VPH = 1/2 VDDCP
–10
IZOUT
Output current variation versus VPH2
VPH in compliance range
–10
ILPH Charge pump off leakage current
VPH = 1/2 VDDCP
–10
VPH Charge pump voltage compliance
0.7 –
MAX.
UNIT
5.5 V
5.5 V
12 mA
– µΑ
2500
0
MHz
dBm
–
–
65535
4
Ω
pF
MHz
550
0
632
–
–
16383
MHz
dBm
mVPP
kΩ
pF
40
1300
–
–
1023
MHz
mVPP
kΩ
pF
15 kΩ
–V
+15
+10
+10
+10
VDDCP–0.8
%
%
%
nA
V
1999 Nov 04
5
5 Page 
Philips Semiconductors
2.5GHz low voltage fractional-N dual frequency
synthesizer
Product specification
SA8026
Serial programming bus
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 8
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the
Serial bus timing characteristics. See Figure 8.
VDD = VDDCP =+3.0V; Tamb = +25°C unless otherwise specified.
SYMBOL
PARAMETER
Serial programming clock; CLK
tr Input rise time
tf Input fall time
Tcy Clock period
Enable programming; STROBE
tSTART
tW
tSU;E
Delay to rising clock edge
Minimum inactive pulse width
Enable set-up time to next clock edge
Register serial input data; DATA
tSU;DAT
tHD;DAT
Input data to clock set-up time
Input data to clock hold time
Application information
tSU;DAT
Tcy
tHD;DAT
data is latched into different working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
sent: C, B, and A. Table 1 shows the format and the contents of
each word. The D word is normally used for testing purposes. When
sending the B-word, data bits FC7–0 for the fractional compensation
DAC are not loaded immediately. Instead they are stored in
temporary registers. Only when the A-word is loaded, these
temporary registers are loaded together with the main divider ratio.
MIN.
–
–
100
40
1/fCOMP
20
20
20
TYP.
10
10
–
–
–
–
–
–
MAX.
40
40
–
–
–
–
–
–
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
tr tf
tSU;E
CLK
DATA
ADDRESS
MSB
LSB
STROBE
tSTART
Figure 8. Serial Bus Timing Diagram
tw
SR01417
1999 Nov 04
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SA8026.PDF ] | |
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