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PDF SA568A Data sheet ( Hoja de datos )

Número de pieza SA568A
Descripción 150MHz phase-locked loop
Fabricantes Philips 
Logotipo Philips Logotipo



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Philips Semiconductors
150MHz phase-locked loop
Product specification
NE/SA568A
DESCRIPTION
The NE568A is a monolithic phase-locked loop (PLL) which
operates from 1Hz to frequencies in excess of 150MHz and features
an extended supply voltage range and a lower temperature
coefficient of the VCO center frequency in comparison with its
predecessor, the NE 568. The NE568A is function and
pin-compatible with the NE568, requiring only minor changes in
peripheral circuitry (see Figure 3). Temperature compensation
network is different, no resistor on Pin 12, needs to be grounded and
Pin 13 has a 3.9kresistor to ground. Timing cap, C2, is different
and for 70MHz operation with temperature compensation network
should be 16pF, not 34pF as was used in the NE568. The NE568A
has the following improvements: ESD protected; extended VCC
range from 4.5V to 5.5V; operating temperature range -55 to 125°C
(see Signetics Military 568A data sheet); less layout sensitivity; and
lower TC of VCO (center frequency). The integrated circuit consists
of a limiting amplifier, a current-controlled oscillator (ICO), a phase
detector, a level shift circuit, V/I and I/V converters, an output buffer,
and bias circuitry with temperature and frequency compensating
characteristics. The design of the NE568A is particularly well-suited
for demodulation of FM signals with extremely large deviation in
systems which require a highly linear output. In satellite receiver
applications with a 70MHz IF, the NE568A will demodulate ±20%
deviations with less than 1.0% typical non-linearity. In addition to
high linearity, the circuit has a loop filter which can be configured
with series or shunt elements to optimize loop dynamic
performance. The NE568A is available in 20-pin dual in-line and
20-pin SO (surface mounted) plastic packages.
FEATURES
Operation to 150MHz
High linearity buffered output
PIN CONFIGURATION
D, N Packages
VCC2 1
GND2 2
GND1 3
TCAP1 4
TCAP2 5
GND1 6
VCC1 7
REFBYP 8
PNPBYP 9
INPBYP 10
20 LF1
19 LF2
18 LF3
17 LF4
16 FREQ ADJ
15 OUTFILT
14 VOUT
13 TCADJ2
12 TCADJ1
11 VIN
TOP VIEW
Figure 1. Pin Configuration
Series or shunt loop filter component capability
External loop gain control
Temperature compensated
ESD protected1
APPLICATIONS
Satellite receivers
Fiber optic video links
VHF FSK demodulators
Clock Recovery
SR01037
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic Small Outline Large (SOL) Package
20-Pin Plastic Dual In-Line Package (DIP)
20-Pin Plastic Small Outline Large (SOL) Package
20-Pin Plastic Dual In-Line Package (DIP)
TEMPERATURE RANGE
0 to +70°C
0 to +70°C
-40 to +85°C
-40 to +85°C
ORDER CODE
NE568AD
NE568AN
SA568AD
SA568AN
DWG #
SOT163-1
SOT146-1
SOT163-1
SOT146-1
BLOCK DIAGRAM
LF1
20
LF2
19
LF3
18
LF4
17
FREQ ADJ OUTFILT VOUT
16 15
14
TCADJ2 TCADJ1 VIN
13 12
11
NOTE:
Pins 4 and 5 can tolerate
1000V only, and all other
pins, greater than 2000V
for ESD (human body
model).
1996 Feb 1
PHASE
DETECTOR
LEVEL SHIFT
V/I
CONVERTER
OUT
BUF
TCADJ BIAS
I/V
CONVERTER
LEVEL SHIFT
AMP
1
VCC2
ICO
2
GND2
3
GND1
4
TCAP1
5
TCAP2
6
GND1
Figure 2. Block Diagram
7
VCC1
89
REFBYP PNPBYP
10
INPBYP
SR01038
1 853-1558 16328

1 page




SA568A pdf
Philips Semiconductors
150MHz phase-locked loop
Product specification
NE/SA568A
NE568A
KT10/89
GND
VCC
VIN
Figure 4. N Package Layout (Not Actual Size)
GND
VCC
VOUT
SR01040
SIGNETICS
NE568A SO
INPUT
OUTPUT
Figure 5. D Package Layout (Not Actual Size)
SR01041
1.25E3
1.0E3
750.0
500.0
ZIN
250.0
0.0
1.0
10.0
100.0
FREQUENCY (MHz)
SR01042
Figure 6. NE568A Input Impedance With CP = 0.5pF 20-Pin SO
Package
1.25E3
1.0E3
750.0
ZIN
500.0
250.0
RIN
0.0
1.0
10.0
100.0
1.0E3
FREQUENCY (MHz)
SR01043
Figure 7. NE568A Input Impedance WithCP = 1.49pF 20-Pin
Dual In-Line Plastic Package
1996 Feb 1
5

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