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PDF SA2532P Data sheet ( Hoja de datos )
| Número de pieza | SA2532P | |
| Descripción | ONE MEMORY SINGLE CHIP TELEPHONE | |
| Fabricantes | Sames | |
| Logotipo |  |
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SA2532P
ONE MEMORY SINGLE
CHIP TELEPHONE
Key Features
• Speech Circuit, LD/MF Dialler and Tone Ringer
on one 28 pin CMOS chip
• Low Noise
• 31 digit Last Number Redial
• Line Loss Compensation selectable by pin
option
• 2 Timed Break Recall keys
• Moving Cursor protocol with comparison
• On chip MF filter (CEPT CS 203 compatible)
• Pause key for auto pause or wait function
• Power down mode
• Ring frequency discrimination
• Selectable Loop-Disconnect or DTMF dialling
modes
• Real or complex impedance programmable
• Soft Clipping to avoid harsh distortion
• Uses inexpensive 3.58MHz ceramic resonator
• Operating range from 13 to 100 mA
• 3 Tone melody generator
Block Diagram
General Description
The SA2532P is a CMOS integrated circuit that
contains all the functions needed to form a high
performance electronic telephone.
The device incorporates LD/MF repertory dialling,
melody generation, ring frequency discrimination
and a high quality speech circuit.
Soft switch into temporary MF mode using * when
LD mode is selected .Timed Break Recall will be
available in both LD and MF dialling modes.
A 31 digit Last Number Redial (LNR) memory, with
moving cursor protocol, activated by single key
depression.
Line Loss Compensation whereby send and receive
gains are adjusted (by 6dB) over the ranges
selected by the LLC pin.
5M1
680n
2K2
La Off
On 4 x 1N4004
Lb
20
12V 100K
220K
Off
On
150K
1M
BSS92
10
30
2N5551
BC327
CS
LI CI
300 6K
+
1u
LS STB
+
10u
RI
Line Adaption
Power Extraction
DC Mask
LINE
CURRENT
SENSE
SA2532P
AGND
BC547B
100K
1N4148
12V
510
Ringer
330K
+
10u
18V
VDD
VDD
VSS
SOFT
CLIP
MO
330K
FC1
220K
10n
+
470u
5V1
MELODY
SEQUENCER
TONE
GENERATOR
RING
FREQUENCY
DISCRIMINATION
CONTROL
LOGIC
OSC
RAM
MUTE
DIALER
HS/DP
MODE
LLC OSC
1K
MODE_OUT
C1 C2 C3 C4
3.58MHz
KEYPAD
2K2
RO1
+
RO2 100u
1K8
10n
M1
M2
10n
1K8
R4
R3
R2
R1
DAT_SH05
PDS039-SA2532P-001 Rev. B 21-03-00
1 page  
SA2532P
Power On Reset
The on chip power on reset circuit monitors the
supply voltage (VDD). When VDD rises above
approx. 1.2V, a power on reset occurs to assure
correct start-up and the LNR register is cleared.
DC Conditions
The normal operating range is from 15mA to 100
mA. Operating range with reduced performance is
from 5mA to 15mA. In the operating range all
functions are operational. In the line hold range
from 0 to 5 mA the device is in a power down mode
and the voltage at LI is reduced to maximum 3.5V.
The dc characteristic (excluding diode bridge and
Pulsing transistors) is determined by the voltage at
LI and the resistor R1 as follows:
VLS = VLI + ILine.R1
The voltage at LI is 4.5V.
During pulse dialling the speech circuit and other
parts of the device not required are in a power
down mode to save current. The CS pin is pulled to
VSS in order to turn the external shunt transistor on
to keep a low voltage drop at the LS pin during
make periods.
AC Impedance
The Characteristic or Output impedance of the
SA2532P is set within the IC and adjusted to 600
Ohms. A capacitor may be added to the circuit at
pin CI to add a reactive element and make the
output impedance complex.
Oscillator
All the Timing Functions of the SA2532P are based
on a Clock Frequency of 3.58MHz. A ceramic
resonator of this frequency should be connected to
the OSC pin. In practice minor deviations from the
nominal frequency may occur due to the
characteristics of the frequency reference device
used and so it is recommended that care is taken in
the selection of components. Typically a small
value capacitor ( ≤ 47pF) may be required to be
connected in parallel with the Frequency Reference
to ensure start-up and/or operation at the nominal
frequency.
Speech Circuit
The speech circuit consists of a transmit and a
receive path with soft clip, mute, line loss
compensation and side tone cancellation.
Transmit
The gain of the transmit path is 35 dB for M1/M2 to
LS (see test circuit in Figure 5). The microphone
input is differential with an input impedance of 25
kOhms. The soft clip circuit limits the output
voltage at LI to 2.0VPEAK. The attack time is
30us/6dB and the decay time is 20 ms/6 dB. When
mute is active, during dialling or after pressing the
MUTE key, the gain is reduced by > 60 dB.
Receive
The receive input is the differential signal of RI and
STB. The gain of the receive path is 2 dB (see test
circuit in Figure 5) with differential outputs,
RO1/RO2 . When mute is active during dialling the
gain is reduced by > 60dB. During DTMF dialling a
MF comfort tone is applied to the receiver. The
comfort tone is the DTMF signal with a level that is
-30dB relative to the line signal.
Side Tone
Side Tone is controlled along with Return Loss by a
Double Balance Bridge as shown in Figure 3. Good
sidetone cancellation is achieved by using the
following equation:
Zbal R5
------ = ----
Zline
R1
The side tone cancellation signal is applied to the
STB input.
Line Loss Compensation
The line loss compensation is a pin selectable
option. When it is activated, the gains of the
transmit and receive amplifiers are changed by 6dB
in accord with the DC conditions as measured at
Pins LI and LS. When the LLC pin is low the
adjustment in gain occurs over the range ILINE = 20
to 50mA. When the LLC pin is high the gain range
is ILINE = 45 to 75mA.. Note that these values apply
for R1 = R30 Ω. When LLC pin is open then the
amplifier gains remain fixed regardless of the line
current.
5 /21 sames
5 Page 
SA2532P
Temporary MF
!
FIFO
RAM
*
FIFO
R
R
FIFO
EXIT FIFO
*
11 /21
sames
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet SA2532P.PDF ] | |
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