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Número de pieza | SA24C1024 | |
Descripción | 1024Kb EEPROM IIC | |
Fabricantes | ETC | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de SA24C1024 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
No Preview Available ! Features
•= Saifun NROM™ NVM Technology
•= Operating voltage: 2.7V to 3.6V
•= Clock frequency: 100/400/1700/3400 kHz
•= Low power consumption
– 0.5µA standby current typical (L version)
– <0.2µA standby current typical (LZ version)
•= Write Modes
– Byte Mode
– Page Mode (128 Bytes/Page)
•= Schmitt trigger inputs
•= Hardware and software write protection for entire or partial array
•= Endurance: up to 1 million data changes
•= Data Retention: Greater than 40 years
•= Packages: 8-Pin DIP and 8-Pin SOIC and MLF Leadless
•= Temperature range
– Commercial: 0 °C to +70 °C
– Industrial (E): -40 °C to +85 °C
SA24C1024
Datasheet
1024Kb EEPROM
IIC
http://www.saifun.com
Saifun NROMTM is a trademark of Saifun Semiconductors Ltd.
This Datasheet states Saifun's current technical specifications regarding the Products described herein. This Datasheet
may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 1908 Rev: 1 Amendment: 1
Issue Date: 26 August 2003
1 page Connection Diagrams
SA24C1024 Datasheet
SAIFUN
5
NC 1
8 VCC
A1 2
7 WP
SA24C1024
NC 3
6 SCL
VSS 4
5 SDA
NC 1
8 VCC
A1 2
7
SA24C1024
NC 3
6 SCL
VSS 4
5 SDA
Figure 2. SO Package (MW), Dual Inline (N) – Top
View
Figure 3. Leadless Package (MLF) – Top View
Note:
For more details, refer to package number N08E and M08D.
Symbol
NC
A1
NC
VSS
SDA
SCL
WP
VCC
Pin Name
Table 1. Pin Names
Description
Not Connected
Device Select Address Input
Pin
Not Connected
Device Ground Input Pin
IIC Data Input/Output Pin
IIC Clock Input Pin
Write Protect
Device Power Input Pin
Has an internal "weak" pulldown, and assumes logic LOW
when left unconnected.
Open Collector/Drain type.
Has an internal "weak" pulldown, and assumes logic LOW
when left unconnected.
When LOW, writing is allowed to the memory array.
When HIGH, writing is not allowed to the memory array, as
defined in Write Protect (WP), page 14.
2.7 V to 3.6 V
Note:
No A2 or A0 pins (Pins 2 and 3) are provided, and are instead treated as Not
Connected. Internal address comparison assumes pin A2 to be 0, and so the
command code should have its corresponding A2 bit set to 0 as well. The
command code should also have its corresponding A0 bit set to add16 (MSB
address bit).
5 Page Write Cycle Timing
SA24C1024 Datasheet
SAIFUN
11
Figure 7. Write Cycle Timing
Note:
The write cycle time (tWR) is the time from a valid STOP condition of a Write
sequence to the end of the internal erase/program cycle.
Typical System Configuration
Figure 8. Typical System Configuration
Note:
Due to the open drain configuration of SDA and SCL, a bus-level pullup resistor
is called for (typical value = 4.7 kΩ).
11 Page |
Páginas | Total 27 Páginas | |
PDF Descargar | [ Datasheet SA24C1024.PDF ] |
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