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PDF S8S3122X16 Data sheet ( Hoja de datos )
| Número de pieza | S8S3122X16 | |
| Descripción | 256K x 16 SDRAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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S8S3122X16
CMOS SDRAM
256K x 16 SDRAM
128K x 16bit x 2 Banks
Synchronous DRAM
LVTTL
Version 0.0
Sep 2001
Samsung Electronics reserves the right to change products or specification without notice.
Ver 0.0 Sep. '01
1 page  
S8S3122X16
CMOS SDRAM
PIN CONFIGURATION (TOP VIEW)
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
BA
A8/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN FUNCTION DESCRIPTION
50 VSS
49 DQ15
48 DQ14
47 VSSQ
46 DQ13
45 DQ12
44 VDDQ
43 DQ11
42 DQ10
41 VSSQ
40 DQ9
39 DQ8
38 VDDQ
37 N.C/RFU
36 UDQM
35 CLK
34 CKE
33 N.C
32 N.C
31 N.C
30 A7
29 A6
28 A5
27 A4
26 VSS
50PIN TSOP (II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
Pin
CLK
CS
Name
System Clock
Chip Select
CKE
Clock Enable
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A8/AP Address
BA Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE Write Enable
L(U)DQM Data Input/Output Mask
DQ0 ~ 15
VDD/VSS
Data Input/Output
Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
N.C/RFU
No Connection/
Reserved for Future Use
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA8, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
Ver 0.0 Sep. '01
5 Page 
S8S3122X16
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
BA
W.B.L
A8/AP
A7
TM
A6 A5 A4
CAS Latency
CMOS SDRAM
A3 A2 A1 A0
BT Burst Length
A8/AP
0
0
1
1
BA
0
1
Test Mode
A7 Type
0 Mode Register Set
1 Reserved
0 Reserved
1 Reserved
Write Burst Length
Length
Burst
Single Bit
CAS Latency
Burst Type
Burst Length
A6 A5 A4 Latency A3
Type
A2 A1 A0 BT = 0 BT = 1
0 0 0 Reserved 0 Sequential 0 0 0
1
1
001
-
1 Interleave 0 0 1
2
2
010
2
01 0
4
4
011
3
01 1
8
8
1 0 0 Reserved
1 0 0 Reserved Reserved
1 0 1 Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved
1 1 0 Reserved Reserved
1 1 1 Reserved
1 1 1 Full Page Reserved
Full Page Length : x4 (512), x8 (256), x16 (256)
POWER UP SEQUENCE
SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. If BA is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
Ver 0.0 Sep. '01
11 Page | ||
| Páginas | Total 44 Páginas | |
| PDF Descargar | [ Datasheet S8S3122X16.PDF ] | |
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