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PDF S83C752-1DB Datasheet ( Hoja de datos )

Número de pieza S83C752-1DB
Descripción 80C51 8-bit microcontroller family 2K/64 OTP/ROM / 5 channel 8 bit A/D / I2C / PWM / low pin count
Fabricantes Philips 
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S83C752-1DB Hoja de datos, Descripción, Manual
INTEGRATED CIRCUITS
83C752/87C752
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM,
low pin count
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Philips
Semiconductors

1 page

S83C752-1DB pdf
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count
Product specification
83C752/87C752
PIN DESCRIPTION
MNEMONIC PIN NO. TYPE
NAME AND FUNCTION
VSS
VCC
P0.0–P0.4
12
28
8–6
23, 24
I Circuit Ground Potential.
I Supply voltage during normal, idle, and power-down operation.
I/O Port 0: Port 0 is a 5-bit bidirectional port. Port 0.0–P0.2 are open drain. Port 0.0–P0.2 pins that have
1s written to them float, and in that state can be used as high-impedance inputs. P0.3–P0.4 are
bidirectional I/O port pins with internal pull-ups. Port 0 also serves as the serial I2C interface. When this
feature is activated by software, SCL and SDA are driven low in accordance with the I2C protocol.
These pins are driven low if the port register bit is written with a 0 or if the I2C subsystem presents a 0.
The state of the pin can always be read from the port register by the program. Port 0.3 and 0.4 have
internal pull-ups that function identically to port 3. Pins that have 1s written to them are pulled high by
the internal pull-ups and can be used as inputs.
To comply with the I2C specification, P0.0 and P0.1 are open drain bidirectional I/O pins with the
electrical characteristics listed in the tables that follow. While these differ from “standard TTL”
characteristics, they are close enough for the pins to still be used as general-purpose I/O in non-I2C
applications.
6 I VPP (P0.2) – Programming voltage input. (See Note 2.)
7 I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
8 I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
P1.0–P1.7
13–17,
20–22
20
21
22
13–17
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. P0.3–P0.4 pins are
bidirectional I/O port pins with internal pull-ups. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also
serves the special function features of the SC80C51 family as listed below:
I INT0 (P1.5): External interrupt.
I INT1 (P1.6): External interrupt.
I T0 (P1.7): Timer 0 external input.
I ADC0 (P1.0)–ADC4 (P1.4): Port 1 also functions as the inputs to the five channel multiplexed A/D
converter. These pins can be used as outputs only if the A/D function has been disabled. These pins
can be used as inputs while the A/D converter is enabled.
Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs the
value to program into the selected address during the program mode.
P3.0–P3.7
5–1,
27–25
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are
externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also functions as the address input for the EPROM memory location to be
programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL.
RST
9 I Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An
internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to VCC.
After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device
in the programming state allowing programming address, data and VPP to be applied for programming
or verification purposes. The RESET serial sequence must be synchronized with the X1 input.
X1 11 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1
also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2 10 O Crystal 2: Output from the inverting oscillator amplifier.
AVCC 1
19 I Analog supply voltage and reference input.
AVSS 1
18 I Analog supply and reference ground.
NOTE:
1. AVSS (reference ground) must be connected to 0V (ground). AVCC (reference input) cannot differ from VCC by more than ±0.2V, and must be
in the range 4.5V to 5.5V.
2. When P0.2 is at or close to 0V, it may affect the internal ROM operation. We recommend that P0.2 be tied to VCC via a small pull-up
(e.g., 2k).
1998 May 01
5

5 Page

S83C752-1DB arduino
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count
Product specification
83C752/87C752
IN+1
SmN+1 RmN+1
SmN
RmN
IN
To Comparator
+
RS
VANALOG
INPUT
Multiplexer
CS
CC
Rm = 0.5 - 3 k
CS + CC = 15pF maximum
RS = Recommended < 9.6 kfor 1 LSB @ 12MHz
NOTE:
Because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. When a conversion
is initiated, switch Sm closes for 8tcy (8µs @ 12MHz crystal frequency) during which time capacitance Cs + Cc is charged. It should
be noted that the sampling causes the analog input to present a varying load to an analog source.
Figure 2. A/D Input: Equivalent Circuit
SU00199
A/D CONVERTER PARAMETER DEFINITIONS
The following definitions are included to clarify some specifications
given and do not represent a complete set of A/D parameter
definitions.
Absolute Accuracy Error
Absolute accuracy error of a given output is the difference between
the theoretical analog input voltage to produce a given output and
the actual analog input voltage required to produce the same code.
Since the same output code is produced by a band of input voltages,
the “required input voltage” is defined as the midpoint of the band of
input voltage that will produce that code. Absolute accuracy error
not specified with a code is the maximum over all codes.
Nonlinearity
If a straight line is drawn between the end points of the actual
converter characteristics such that zero offset and full scale errors
are removed, then non-linearity is the maximum deviation of the
code transitions of the actual characteristics from that of the straight
line so constructed. This is also referred to as relative accuracy and
also integral non-linearity.
Differential Non-Linearity
Differential non-linearity is the maximum difference between the
actual and ideal code widths of the converter. The code widths are
the differences expressed in LSB between the code transition
points, as the input voltage is varied through the range for the
complete set of codes.
Gain Error
Gain error is the deviation between the ideal and actual analog input
voltage required to cause the final code transition to a full-scale
output code after the offset error has been removed. This may
sometimes be referred to as full scale error.
Offset Error
Offset error is the difference between the actual input voltage that
causes the first code transition and the ideal value to cause the first
code transition. This ideal value is 1/2 LSB above Vref–.
Channel to Channel Matching
Channel to channel matching is the maximum difference between
the corresponding code transitions of the actual characteristics
taken from different channels under the same temperature, voltage
and frequency conditions.
Crosstalk
Crosstalk is the measured level of a signal at the output of the
converter resulting from a signal applied to one deselected channel.
Total Error
Maximum deviation of any step point from a line connecting the ideal
first transition point to the ideal last transition point.
Relative Accuracy
Relative accuracy error is the deviation of the ADC’s actual code
transition points from the ideal code transition points on a straight
line which connects the ideal first code transition point and the final
code transition point, after nullifying offset error and gain error. It is
generally expressed in LSBs or in percent of FSR.
1998 May 01
11

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