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PDF S80C552-BA68 Data sheet ( Hoja de datos )

Número de pieza S80C552-BA68
Descripción Single-chip 8-bit microcontroller
Fabricantes Philips 
Logotipo Philips Logotipo



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No Preview Available ! S80C552-BA68 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
80C552/83C552
Single-chip 8-bit microcontroller
Product specification
Supersedes data of 1998 Jan 06
IC20 Data Handbook
1998 Aug 13
Philips
Semiconductors

1 page




S80C552-BA68 pdf
Philips Semiconductors
Single-chip 8-bit microcontroller
Product specification
80C552/83C552
BLOCK DIAGRAM
T0 T1
33
INT0 INT1
33
VDD
VSS
PWM0
PWM1
AVSS AVREF ADC0-7 SDA SCL
–+
AVDD STADC
51 1
XTAL1
XTAL2
EA
ALE
PSEN
3
WR
3
RD
0
AD0-7
2
A8-15
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
CPU
80C51 CORE
EXCLUDING
ROM/RAM
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
PROGRAM
MEMORY
8k x 8 ROM
DATA
MEMORY
256 x 8 RAM
DUAL
PWM
ADC
SERIAL
I2C PORT
8-BIT INTERNAL BUS
16
8-BIT
PORT
FOUR
16-BIT
CAPTURE
LATCHES
T2
16-BIT
TIMER/
EVENT
COUNTERS
16
T2
16-BIT
COMPARA-
TORS
wITH
REGISTERS
COMPARA-
TOR
OUTPUT
SELECTION
T3
WATCHDOG
TIMER
33
P0 P1 P2 P3 TxD RxD
P5 P4
1
CT0I-CT3I
1
T2
1
RT2
0 ALTERNATE FUNCTION OF PORT 0
1 ALTERNATE FUNCTION OF PORT 1
2 ALTERNATE FUNCTION OF PORT 2
3 ALTERNATE FUNCTION OF PORT 3
4 ALTERNATE FUNCTION OF PORT 4
5 ALTERNATE FUNCTION OF PORT 5
4
CMSR0-CMSR5 RST EW
CMT0, CMT1
1998 Aug 13
5

5 Page





S80C552-BA68 arduino
Philips Semiconductors
Single-chip 8-bit microcontroller
Product specification
80C552/83C552
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Analog Inputs
AIDD
Analog supply current: operating: (16MHz)
Analog supply current: operating: (24MHz, 30MHz)
Port 5 = 0 to AVDD
Port 5 = 0 to AVDD
1.2 mA
1.0 mA
AIID Idle mode:
P83(0)C552EBx
P83(0)C552EFx
P83(0)C552EHx
P83(0)C552IBx
P83(0)C552IFx
P83(0)C552KBx
50 µA
50 µA
100 µA
50 µA
50 µA
50 µA
AIPD
Power-down mode:
P83(0)C552xBx
P83(0)C552xFx
P83(0)C552xHx
2V < AVPD < AVDD max
50 µA
50 µA
100 µA
AVIN
Analog input voltage
AVSS–0.2 AVDD+0.2
V
AVREF
Reference voltage:
AVREF–
AVREF+
AVSS–0.2
AVDD+0.2
V
V
RREF
Resistance between AVREF+ and AVREF–
10 50 k
CIA Analog input capacitance
15 pF
tADS
Sampling time
8tCY
µs
tADC
Conversion time (including sampling time)
50tCY
µs
DLe Differential non-linearity10, 11, 12
±1 LSB
ILe Integral non-linearity10, 13
±2 LSB
OSe
Ge
Offset error10, 14
Gain error10, 15
±2 LSB
±0.4 %
Ae Absolute voltage error10, 16
±3 LSB
MCTC
Channel to channel matching
±1 LSB
Ct Crosstalk between inputs of port 517
0–100kHz
–60 dB
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 10 through 15 for IDD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V;
VIH = VDD – 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V;
VIH = VDD – 0.5V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD;
EA = RST = STADC = XTAL1 = VSS.
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5V will be recognized as a logic
0 while an input voltage above 3.0V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when VIN is approximately 2V.
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the
address bits are stabilizing.
9. The following condition must not be exceeded: VDD – 0.2V < AVDD < VDD + 0.2V.
10. Conditions: AVREF– = 0V; AVDD = 5.0V, AVREF+ (80C552, 83C552) = 5.12V. ADC is monotonic with no missing codes. Measurement by
continuous conversion of AVIN = –20mV to 5.12V in steps of 0.5mV.
11. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 1.)
12. The ADC is monotonic; there are no missing codes.
1998 Aug 13
11

11 Page







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