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PDF P51XAG33KFBD Data sheet ( Hoja de datos )

Número de pieza P51XAG33KFBD
Descripción XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless / watchdog / 2 UARTs
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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INTEGRATED CIRCUITS
XA-G3
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
Product specification
Supersedes data of 1998 Aug 14
IC25 Data Handbook
1999 Apr 07
Philips
Semiconductors

1 page




P51XAG33KFBD pdf
Philips Semiconductors
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
Product specification
XA-G3
PIN DESCRIPTIONS
PIN. NO.
MNEMONIC
TYPE
PLCC LQFP
NAME AND FUNCTION
VSS
VDD
P0.0 – P0.7
1, 22
23, 44
43–36
16
17
37–30
I Ground: 0V reference.
I Power Supply: This is the power supply voltage for normal, idle, and power down operation.
I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches have 1s
written to them and are configured in the quasi-bidirectional mode during reset. The operation of
port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
When the external program/data bus is used, Port 0 becomes the multiplexed low data/instruction
byte and address lines 4 through 11.
P1.0 – P1.7 2–9 40–44, I/O Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type. Port 1 latches have 1s
1–3 written to them and are configured in the quasi-bidirectional mode during reset. The operation of
port 1 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
Port 1 also provides special functions as described below.
2 40 O
A0/WRH:
Address bit 0 of the external address bus when the external data bus is
configured for an 8 bit width. When the external data bus is configured for a 16
bit width, this pin becomes the high byte write strobe.
3 41 O
4 42 O
A1:
A2:
Address bit 1 of the external address bus.
Address bit 2 of the external address bus.
5 43 O
6 44 I
7 1O
A3:
RxD1 (P1.4):
TxD1 (P1.5):
Address bit 3 of the external address bus.
Receiver input for serial port 1.
Transmitter output for serial port 1.
8
2
I/O
T2 (P1.6):
Timer/counter 2 external count input/clockout.
9 3 I T2EX (P1.7): Timer/counter 2 reload/capture/direction control
P2.0 – P2.7 24–31 18–25
I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s
written to them and are configured in the quasi-bidirectional mode during reset. The operation of
port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
When the external program/data bus is used in 16-bit mode, Port 2 becomes the multiplexed high
data/instruction byte and address lines 12 through 19. When the external program/data bus is used in
8-bit mode, the number of address lines that appear on port 2 is user programmable.
P3.0 – P3.7 11,
5,
13–19 7–13
11 5
13 7
14 8
15 9
16 10
17 11
18 12
19 13
I/O Port 3: Port 3 is an 8-bit I/O port with a user configurable output type. Port 3 latches have 1s
written to them and are configured in the quasi-bidirectional mode during reset. the operation of
port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
Port 3 also provides various special functions as described below.
I
RxD0 (P3.0):
Receiver input for serial port 0.
O
TxD0 (P3.1):
Transmitter output for serial port 0.
I
INT0 (P3.2):
External interrupt 0 input.
I
INT1 (P3.3):
External interrupt 1 input.
I/O T0 (P3.4):
Timer 0 external input, or timer 0 overflow output.
I/O T1/BUSW (P3.5): Timer 1 external input, or timer 1 overflow output. The value on this pin is
latched as the external reset input is released and defines the default
external data bus width (BUSW). 0 = 8-bit bus and 1 = 16-bit bus.
O WRL (P3.6): External data memory low byte write strobe.
O RD (P3.7):
External data memory read strobe.
RST
10 4
I Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on
their default states, and the processor to begin execution at the address contained in the reset
vector. Refer to the section on Reset for details.
ALE/PROG 33 27 I/O Address Latch Enable/Program Pulse: A high output on the ALE pin signals external circuitry to
latch the address portion of the multiplexed address/data bus. A pulse on ALE occurs only when it
is needed in order to process a bus cycle.
1999 Apr 07
5

5 Page





P51XAG33KFBD arduino
Philips Semiconductors
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
Product specification
XA-G3
T2CON Address:418
Bit Addressable
Reset Value: 00H
MSB
TF2
EXF2 RCLK0 TCLK0 EXEN2 TR2
LSB
C/T2 CP/RL2
BIT
T2CON.7
T2CON.6
T2CON.5
T2CON.4
T2CON.3
T2CON.2
T2CON.1
T2CON.0
SYMBOL
TF2
EXF2
RCLK0
TCLK0
EXEN2
TR2
C/T2
CP/RL2
FUNCTION
Timer 2 overflow flag. Set by hardware on Timer/Counter overflow. Must be cleared by software.
TF2 will not be set when RCLK0, RCLK1, TCLK0, TCLK1 or T2OE=1.
Timer 2 external flag is set when a capture or reload occurs due to a negative transition on T2EX (and
EXEN2 is set). This flag will cause a Timer 2 interrupt when this interrupt is enabled. EXF2 is cleared by
software.
Receive Clock Flag.
Transmit Clock Flag. RCLK0 and TCLK0 are used to select Timer 2 overflow rate as a clock source for
UART0 instead of Timer T1.
Timer 2 external enable bit allows a capture or reload to occur due to a negative transition on T2EX.
Start=1/Stop=0 control for Timer 2.
Timer or counter select.
0=Internal timer
1=External event counter (falling edge triggered)
Capture/Reload flag.
If CP/RL2 & EXEN2=1 captures will occur on negative transitions of T2EX.
If CP/RL2=0, EXEN2=1 auto reloads occur with either Timer 2 overflows or negative transitions at T2EX.
If RCLK or TCLK=1 the timer is set to auto reload on Timer 2 overflow, this bit has no effect.
SU00606A
Figure 4. Timer/Counter 2 Control (T2CON) Register
New Timer-Overflow Toggle Output
In the XA, the timer module now has two outputs, which toggle on
overflow from the individual timers. The same device pins that are
used for the T0 and T1 count inputs are also used for the new
overflow outputs. An SFR bit (TnOE in the TSTAT register) is
associated with each counter and indicates whether Port-SFR data
or the overflow signal is output to the pin. These outputs could be
used in applications for generating variable duty cycle PWM outputs
(changing the auto-reload register values). Also variable frequency
(Osc/8 to Osc/8,388,608) outputs could be achieved by adjusting
the prescaler along with the auto-reload register values. With a
30.0MHz oscillator, this range would be 3.58Hz to 3.75MHz.
Timer T2
Timer 2 in the XA is a 16-bit Timer/Counter which can operate as
either a timer or as an event counter. This is selected by C/T2 in the
special function register T2CON. Upon timer T2 overflow/underflow,
the TF2 flag is set, which may be used to generate an interrupt. It
can be operated in one of three operating modes: auto-reload (up or
down counting), capture, or as the baud rate generator (for either or
both UARTs via SFRs T2MOD and T2CON). These modes are
shown in Table 1.
Capture Mode
In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, then timer 2 is a 16-bit timer or
counter, which upon overflowing sets bit TF2, the timer 2 overflow
bit. This will cause an interrupt when the timer 2 interrupt is enabled.
If EXEN2 = 1, then Timer 2 still does the above, but with the added
feature that a 1-to-0 transition at external input T2EX causes the
current value in the Timer 2 registers, TL2 and TH2, to be captured
into registers RCAP2L and RCAP2H, respectively. In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set. This will
cause an interrupt in the same fashion as TF2 when the Timer 2
interrupt is enabled. The capture mode is illustrated in Figure 7.
Auto-Reload Mode (Up or Down Counter)
In the auto-reload mode, the timer registers are loaded with the
16-bit value in T2CAPH and T2CAPL when the count overflows.
T2CAPH and T2CAPL are initialized by software. If the EXEN2 bit in
T2CON is set, the timer registers will also be reloaded and the EXF2
flag set when a 1-to-0 transition occurs at input T2EX. The
auto-reload mode is shown in Figure 8.
In this mode, Timer 2 can be configured to count up or down. This is
done by setting or clearing the bit DCEN (Down Counter Enable) in
the T2MOD special function register (see Table 1). The T2EX pin
then controls the count direction. When T2EX is high, the count is in
the up direction, when T2EX is low, the count is in the down
direction.
Figure 8 shows Timer 2, which will count up automatically, since
DCEN = 0. In this mode there are two options selected by bit
EXEN2 in the T2CON register. If EXEN2 = 0, then Timer 2 counts
up to FFFFH and sets the TF2 (Overflow Flag) bit upon overflow.
This causes the Timer 2 registers to be reloaded with the 16-bit
value in T2CAPL and T2CAPH, whose values are preset by
software. If EXEN2 = 1, a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. If enabled, either TF2 or EXF2 bit can generate
the Timer 2 interrupt.
In Figure 9, the DCEN = 1; this enables the Timer 2 to count up or
down. In this mode, the logic level of T2EX pin controls the direction
of count. When a logic ‘1’ is applied at pin T2EX, the Timer 2 will
count up. The Timer 2 will overflow at FFFFH and set the TF2 flag,
which can then generate an interrupt if enabled. This timer overflow,
also causes the 16-bit value in T2CAPL and T2CAPH to be
reloaded into the timer registers TL2 and TH2, respectively.
A logic ‘0’ at pin T2EX causes Timer 2 to count down. When
counting down, the timer value is compared to the 16-bit value
contained in T2CAPH and T2CAPL. When the value is equal, the
1999 Apr 07
11

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