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PDF P4C1024-17J4C Datasheet ( Hoja de datos )

Número de pieza P4C1024-17J4C
Descripción HIGH SPEED 128K X 8 CMOS STATIC RAM
Fabricantes ETC 
Logotipo ETC Logotipo

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P4C1024-17J4C Hoja de datos, Descripción, Manual
P4C1024
HIGH SPEED 128K x 8
CMOS STATIC RAM
P4C1024
FEATURES
High Speed (Equal Access and Cycle Times)
— 15/17/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
Single 5 Volts ±10% Power Supply
Easy
Memory
Expansion
Using
CE
1,
CE2
and
OE Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
DESCRIPTION
The P4C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 15 nanoseconds permit greatly en-
hanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1024
is a member of a family of PACE RAM™ products offer-
ing fast access times.
The P4C1024 device provides asynchronous opera-
tions with matching access and cycle times. Memory
locations are specified on address pins A0 to A16. Read-
ing is accomplished by device selection (CE low and
1
CE high) and output enabling (OE) while write enable
2
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is
HIGH
or
WE
or
CE2
is
LOW.
Package options for the P4C1024 include 32-pin 300
mil DIP and SOJ packages as well as 400 mil SOJ.
FUNCTIONAL BLOCK DIAGRAM
A
(9)
A
I/O1
I/O2
INPUT
DATA
CONTROL
262,144-
BIT
MEMORY
ARRAY
COLUMN
I/O
WE
CE1
CE2
OE
CONTROL
CIRCUIT
COLUMN
SELECT
••• •••
A (8)
A
1024.1
PIN CONFIGURATION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
1024.2
DIP (P300), SOJ (J300, J400)
TOP VIEW
Means Quality, Service and Speed
1Q97
141

1 page

P4C1024-17J4C pdf
P4C1024
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
-15 -17 -20 -25 -35 -45
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time 15 17 20 25 35 45
ns
t Chip Enable Time 12 13 15 18 22 30
CW
to End of Write
tAW Address Valid to 12 13 15 20 25 35
End of Write
ns
ns
tAS Address Set-up 0 0 0 0 0 0
Time
tWP Write Pulse Width 12 12 15 18 22 25
ns
ns
t
AH
Address Hold Time 0
0
00
0
0
ns
t Data Valid to End 7
7 8 10 15 20 ns
DW
of Write
tDH Data Hold Time 0 0 0 0 0 0 ns
tWZ Write Enable to
Output in High Z
8 8 10 11 15 18 ns
tOW Output Active from 3
End of Write
3 33 3 3
ns
WRITE CYCLE NO. 1 (WE CONTROLLED)(6)
ADDRESS
CE1
CE2
WE
DATA IN
(7)
DATA OUT
tCW
t AW
t AS
DATA UNDEFINED
tWZ(4)
(9)
t WC
tWP
tAH
t DW
DATA VALID
tDH
t OW (4,7)
HIGH IMPEDANCE
Notes:
6.
CE
1
and
WE
are
LOW
and
CE2
is
HIGH
for
WRITE
cycle.
7. OE is LOW for this WRITE cycle to show twz and tow.
8.
If
CE
1
goes
HIGH
or
CE2
goes
LOW
simultaneously
with
WE
HIGH,
the
output
remains
in
a
high
impedance
state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
145

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