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PDF P32P4911A Datasheet ( Hoja de datos )

Número de pieza P32P4911A
Descripción PRML Read Channel with PR4 / 8/9 ENDEC / FWR Servo
Fabricantes NXP 
Logotipo NXP Logotipo

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P32P4911A Hoja de datos, Descripción, Manual
INTEGRATED CIRCUITS
DATA SHEET
P32P4911A
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
Product Specification
1996 Jul 25

1 page

P32P4911A pdf
Philips Semiconductors
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
Product specification
P32P4911A
Time Base Generator:
Less than 1% frequency resolution
Up to 141 MHz frequency output
Independent M and N divide-by registers
No active external components required
Data Separator:
Fully integrated data separator includes data synchronizer and 8,9 GCR ENDEC
Register programmable to 125 Mbit/s operation
Fast Acquisition, sampled data phase lock loop
Decision directed clock recovery from data samples
Adaptive clock recovery thresholds
Programmable damping ratio for data synchronizer PLL is constant for all data rates
Data scrambler/descrambler to reduce fixed pattern effects
4-bit nibble and byte-wide NRZ data interfaces
Nibble clock is available during byte-wide mode
Time base tracking, programmable write precompensation
Differential PECL write data output
Integrated sync byte detection, single byte or dual ("or" type)
Semi-auto training and sync byte generation available for single sync byte operation
Surface defect scan mode
Servo:
Wide bandwidth, precision full-wave rectifier
Separate, automatically selected, registers for servo ƒc, boost, and threshold
SEROUT and SREF pins to provide a differential full-wave rectified servo signal
SELVRC and SDIEN control pins for dc gain and offset calibration
AGCREF output to provide 2-bit DAC-controlled voltage for applications requiring a fixed gain in servo mode
1996 Jul 25
5

5 Page

P32P4911A arduino
Philips Semiconductors
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
Product specification
P32P4911A
Pulse Qualification Circuit Descriptions
This device utilizes three different types of pulse qualification, one exclusively for servo reads, one primarily for servo
reads, and the other for data reads.
SERVO READ MODE
For servo gray code reads, either a dual level (window type) qualifier or a hysteresis type level qualifier may be selected.
If the PDM bit in the Servo Filter Cutoff Register is set to 0, then the window qualifier is selected, and if the PDM bit is a
1, the hysteresis qualifier is selected. The polarity of the RDS/RDS is selected by the SMS bit (Servo Mode Select) in
the Data Rate Register. If SMS=0 then RDS is active-Low and if SMS=1 then RDS is active-High.
DUAL LEVEL (WINDOW) QUALIFIER
During servo reads (SG High) a dual level type of pulse qualifier is used. The level qualification thresholds are set by a
6-bit DAC which is controlled by the Servo Level Threshold Register (LDS). The register value is relative to the peak
voltage at the output of the continuous time filter, derived off of the same reference voltage internal to the chip. The
positive and negative thresholds are equal in magnitude. The state of the adaptive threshold level enable (ALE) bit in
the WP/LT Register does not affect this DAC's reference. The RDS/RDS and the PPOL outputs of the level qualifier
indicate a qualified servo pulse and the polarity of the pulse, respectively. The RDS/RDS and PPOL outputs are only
active when the SG input is High.
HYSTERESIS QUALIFIER
The hysteresis qualifier performs the same as the window qualifier except that the hysteresis qualifier guarantees that
the second of two consecutive pulses of the same polarity will not be qualified. The hysteresis qualifier will only qualify
pulses of alternating polarity.
DATA READ MODE
In data read mode (RG High), the dual level qualifier used for servo reads, is used during VCO sync field counting. Its
qualification thresholds are set by a 6-bit DAC which is controlled by the Data Level Threshold Register (LD). The
register value is relative to the peak voltage at output of the continuous time filter and the DAC both referenced to band
gap voltage. The positive and negative thresholds are equal in magnitude. The state of the adaptive threshold level
enable (ALE) bit in the WP/LT Register does not affect the DAC's reference until the sync field count has been achieved.
The RDS/RDS and the PPOL outputs of the level qualifier are not active in data read mode.
VITERBI QUALIFIER
The second type of pulse qualification, the Viterbi qualifier, is only used during data read mode after the sync field count
has been achieved. The Viterbi qualifier has two significant blocks, one that feeds the other. The first block is the
sampled pulse detector and the second is the survival sequence register.
The sampled pulse detector performs the pulse acquisition/detection in the sampled domain. It acquires pulses by
comparing the code clock sampled analog waveform to the positive and negative thresholds established by the
programmable Viterbi threshold window. The threshold window is defined to be the difference between the positive and
negative threshold levels. The threshold window, Vth, is set by a 7-bit DAC which is controlled by the Viterbi Detector
Threshold Register (VDT). While the window size is fixed by the programmed Vth value, the actual positive and negative
thresholds track the most positive and the most negative samples of the equalized input signal. For example, the Viterbi
positive signal threshold, Vpt = Vpeak (+) max if the previous detected level was (+). If the previous detect level was (-),
Vpt = Vpeak(-)max + Vth, where Vpeak(-)max is the maximum amplitude of the previously detected negative signal.
Normally Vth is set to equal Vpeak (approx. 500 mV).
After the pulses have been detected they must be further qualified by the survival sequence registers and associated
logic. This logic guarantees that for sequential pulses of the same polarity within the maximum run length, only the latest
is qualified. In this way, only the pulse of greatest amplitude will be qualified.
1996 Jul 25
11

11 Page


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