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PDF P2V28S20ATP-8 Data sheet ( Hoja de datos )

Número de pieza P2V28S20ATP-8
Descripción 128Mb SDRAM Specification
Fabricantes Vanguard International Semiconductor 
Logotipo Vanguard International Semiconductor Logotipo



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No Preview Available ! P2V28S20ATP-8 Hoja de datos, Descripción, Manual

128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
128Mb SDRAM Specification
P2V28S20DTP-7,-75,-8
P2V28S30DTP-7,-75,-8
P2V28S40DTP-7,-75,-8
JULY.2000
MIRA TECHNOLOGY INC.
8F.,68,SEC.3,NANKING E.RD.,TAIPEI,TAIWAN,R.O.C.
TEL:886-2-25170055.25170066
FAX:886-2-25174575
Rev.2.2

1 page




P2V28S20ATP-8 pdf
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
PIN FUNCTION
CLK
Input
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-11
Input
Master Clock:
All other inputs are referenced to the rising edge of CLK
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
Chip Select:
When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11.
The Column Address is specified by A0-9,11(x4)/A0-9(x8)/A0-8(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
BA0,1
Input
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
Input / Output Data In and Data out are referenced to the rising edge of CLK.
DQM(x4,x8),
DQMU/L(x16)
Input
Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Vdd, Vss
VddQ, VssQ
Power Supply Power Supply for the memory array and peripheral circuitry.
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
JULY.2000
Page-4
Rev.2.2

5 Page





P2V28S20ATP-8 arduino
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command Action
PRE -
H X X XX
CHARGING
L H H HX
DESEL NOP (Idle after tRP)
NOP NOP (Idle after tRP)
L H H L BA
TBST ILLEGAL*2
LH
READ /
L X BA, CA, A10 WRITE ILLEGAL*2
L L H H BA, RA
ACT ILLEGAL*2
L L H L BA, A10
PRE /
NOP*4 (Idle after tRP)
PREA
L L L HX
Op-Code,
L L L L Mode-Add
REFA ILLEGAL
MRS ILLEGAL
ROW
H X X XX
ACTIVATING
L H H HX
DESEL NOP (Row Active after tRCD)
NOP NOP (Row Active after tRCD)
L H H L BA
TBST ILLEGAL*2
LH
READ /
L X BA, CA, A10
ILLEGAL*2
WRIT E
L L H H BA, RA
ACT ILLEGAL*2
L L H L BA, A10
PRE /
PREA ILLEGAL*2
L L L HX
Op-Code,
L L L L Mode-Add
REFA ILLEGAL
MRS ILLEGAL
JULY.2000
Page-10
Rev.2.2

11 Page







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