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PDF P28F001BX-B90 Data sheet ( Hoja de datos )

Número de pieza P28F001BX-B90
Descripción 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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1-MBIT (128K x 8)
BOOT BLOCK FLASH MEMORY
28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B
Y High-Integration Blocked Architecture
One 8 KB Boot Block w Lock Out
Two 4 KB Parameter Blocks
One 112 KB Main Block
Y 100 000 Erase Program Cycles Per
Block
Y Simplified Program and Erase
Automated Algorithms via On-Chip
Write State Machine (WSM)
Y SRAM-Compatible Write Interface
Y Deep Power-Down Mode
0 05 mA ICC Typical
0 8 mA IPP Typical
Y 12 0V g5% VPP
Y High-Performance Read
70 75 ns 90 ns 120 ns 150 ns
Maximum Access Time
5 0V g10% VCC
Y Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y Advanced Packaging JEDEC Pinouts
32-Pin PDIP
32-Lead PLCC TSOP
Y ETOXTM II Nonvolatile Flash
Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
Y Extended Temperature Options
Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with
features that simplify write and allow block erase These devices aid the system designer by combining the
functions of several components into one making boot block flash an innovative alternative to EPROM and
EEPROM or battery-backed static RAM Many new and existing designs can take advantage of the
28F001BX’s integration of blocked architecture automated electrical reprogramming and standard processor
interface
The 28F001BX-B and 28F001BX-T are 1 048 576 bit nonvolatile memories organized as 131 072 bytes of
8 bits They are offered in 32-pin plastic DIP 32-lead PLCC and 32-lead TSOP packages Pin assignment
conform to JEDEC standards for byte-wide EPROMs These devices use an integrated command port and
state machine for simplified block erasure and byte reprogramming The 28F001BX-T’s block locations pro-
vide compatibility with microprocessors and microcontrollers that boot from high memory such as Intel’s
MCS -186 family 80286 i386TM i486TM i860TM and 80960CA With exactly the same memory segmentation
the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory
such as Intel’s MCS-51 MCS-196 80960KX and 80960SX families All other features are identical and unless
otherwise noted the term 28F001BX can refer to either device throughout the remainder of this document
The boot block section includes a reprogramming write lock out feature to guarantee data integrity It is
designed to contain secure code which will bring up the system minimally and download code to the other
locations of the 28F001BX Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring high-
performance access speeds low power consumption and immunity to noise Its access time provides
no-WAIT-state performance for a wide range of microprocessors and microcontrollers A deep-powerdown
mode lowers power consumption to 0 25 mW typical through VCC crucial in laptop computer handheld instru-
mentation and other low-power applications The RP power control input also provides absolute data protec-
tion during system powerup or power loss
Manufactured on Intel’s ETOX process base the 28F001BX builds on years of EPROM experience to yield the
highest levels of quality reliability and cost-effectiveness
NOTE The 28F001BN is equivalent to the 28F001BX
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290406-007

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P28F001BX-B90 pdf
28F001BX-T 28F001BX-B
Reprogrammable environments such as the per-
sonal computer are ideal applications for the
28F001BX The internal state machine provides
SRAM-like timings for program and erasure using
the Command and Status Registers The blocking
scheme allows BIOS update in the main and param-
eter blocks while still providing recovery code in the
boot block in the unlikely event a power failure oc-
curs during an update or where BIOS code is cor-
rupted Parameter blocks also provide convenient
configuration storage backing up SRAM and battery
configurations EISA systems for example can
store hardware configurations in a flash parameter
block reducing system SRAM
Laptop BIOSs are becoming increasingly complex
with the addition of power management software
and extended system setup screens BIOS code
complexity increases the potential for code updates
after the sale but the compactness of laptop de-
signs makes hardware updates very costly Boot
block flash memory provides an inexpensive update
solution for laptops while reducing laptop obsoles-
cence For portable PCs and hand-held equipment
the deep powerdown mode dramatically lowers sys-
tem power requirements during periods of slow op-
eration or sleep modes
The 28F001BX gives the embedded system design-
er several desired features The internal state ma-
chine reduces the size of external code dedicated to
the erase and program algorithms as well as freeing
the microcontroller or microprocessor to respond to
other system requests during program and erasure
The four blocks allow logical segmentation of the
entire embedded software the 8-KByte block for the
boot code the 112-KByte block for the main pro-
gram code and the two 4-KByte blocks for updatable
parametric data storage diagnostic messages and
data or extensions of either the boot code or pro-
gram code The boot block is hardware protected
against unauthorized write or erase of its vital code
in the field Further the powerdown mode also locks
out erase or write operations providing absolute
data protection during system powerup or power
loss This hardware protection provides obvious ad-
vantages for safety related applications such as
transportation military and medical The 28F001BX
is well suited for minimum-chip embedded applica-
tions ranging from communications to automotive
290406 – 5
Figure 5 28F001BX-T in a 80C188 System
290406 – 6
Figure 6 28F001BX-B in a 80C51 System
5

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P28F001BX-B90 arduino
28F001BX-T 28F001BX-B
Program Setup Program Commands
Programming is executed by a two-write sequence
The program Setup command (40H) is written to the
Command Register followed by a second write
specifying the address and data (latched on the ris-
ing edge of WE ) to be programmed The WSM
then takes over controlling the program and verify
algorithms internally After the two-command pro-
gram sequence is written to it the 28F001BX auto-
matically outputs Status Register data when read
(see Figure 9 Byte Program Flowchart) The CPU
can detect the completion of the program event by
analyzing the WSM Status bit of the Status Register
Only the Read Status Register command is valid
while programming is active
When the Status Register indicates that program-
ming is complete the Program Status bit should be
checked If program error is detected the Status
Register should be cleared The internal WSM verify
only detects errors for ‘‘1s’’ that do not successfully
program to ‘‘0s’’ The Command Register remains in
Read Status Register mode until further commands
are issued to it If byte program is attempted while
VPP e VPPL the VPP Status bit will be set to ‘‘1’’
Program attempts while VPPL k VPP k VPPH pro-
duce spurious results and should not be attempted
EXTENDED ERASE PROGRAM
CYCLING
EEPROM cycling failures have always concerned
users The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions To combat this some sup-
pliers have implemented redundancy schemes re-
ducing cycling failures to insignificant levels Howev-
er redundancy requires that cell size be doubled an
expensive solution
Intel has designed extended cycling capability into
its ETOX flash memory technology Resulting im-
provements in cycling reliability come without in-
creasing memory cell size or complexity First an
advanced tunnel oxide increases the charge carry-
ing ability ten-fold Second the oxide area per cell
subjected to the tunneling electrical field is one-
tenth that of common EEPROMs minimizing the
probability of oxide defects in the region Finally the
peak electric field during erasure is approximately 2
Mv cm lower than EEPROM The lower electric field
greatly reduces oxide stress and the probability of
failure
The 28F001BX-B and 28F001BX-T are capable of
100 000 program erase cycles on each parameter
block main block and boot block
ON-CHIP PROGRAMMING
ALGORITHM
The 28F001BX integrates the Quick Pulse program-
ming algorithm of prior Intel Flash Memory devices
on-chip using the Command Register Status Regis-
ter and Write State Machine (WSM) On-chip inte-
gration dramatically simplifies system software and
provides processor-like interface timings to the
Command and Status Registers WSM operation in-
ternal program verify and VPP high voltage presence
are monitored and reported via appropriate Status
Register bits Figure 9 shows a system software
flowchart for device programming The entire se-
quence is performed with VPP at VPPH Program
abort occurs when RP transitions to VIL or VPP
drops to VPPL Although the WSM is halted byte
data is partially programmed at the location where
programming was aborted Block erasure or a re-
peat of byte programming will initialize this data to a
known value
ON-CHIP ERASE ALGORITHM
As above the Quick Erase algorithm of prior Intel
Flash Memory devices is now implemented internal-
ly including all preconditioning of block data WSM
operation erase success and VPP high voltage pres-
ence are monitored and reported through the Status
Register Additionally if a command other than
Erase Confirm is written to the device after Erase
Setup has been written both the Erase Status and
Program Status bits will be set to ‘‘1’’ When issuing
the Erase Setup and Erase Confirm commands they
should be written to an address within the address
range of the block to be erased Figure 10 shows a
system software flowchart for block erase
Erase typically takes 1 – 4 seconds per block The
Erase Suspend Erase Resume command sequence
allows interrupt of this erase operation to read data
from a block other than that in which erase is
being performed A system software flowchart is
shown in Figure 11
The entire sequence is performed with VPP at VPPH
Abort occurs when RP transitions to VIL or VPP
falls to VPPL while erase is in progress Block data is
partially erased by this operation and a repeat of
erase is required to obtain a fully erased block
11

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