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PDF OZ6933 Data sheet ( Hoja de datos )

Número de pieza OZ6933
Descripción ACPI CardBus Controller
Fabricantes ETC 
Logotipo ETC Logotipo



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FEATURES
ACPI-PCI Bus Power Management Interface
Specification Rev 1.1 Compliant
Supports OnNow LAN wakeup, OnNow Ring Indicate,
PCI CLKRUN#, PME#, and CardBus CCLKRUN#
Compliant with PCI specification v2.2, 2000 PC Card
Standard 7.1
Yenta™ PCI to PCMCIA CardBus Bridge register
compatible
ExCA (Exchangeable Card Architecture) compatible
registers mappable in memory and I/O space
IntelTM 82365SL PCIC Register Compatible
Supports PCMCIA_ATA Specification
Supports 5V/3.3V PC Cards and 3.3V CardBus cards
Supports two PC Card or CardBus slots with hot
insertion and removal
Supports multiple FIFOs for PCI/CardBus data transfer
Supports Direct Memory Access for PC/PCI and
PCI/Way on PC Card socket
Programmable interrupt protocol: PCI, PCI+ISA,
PCI/Way, or PC/PCI interrupt signaling modes
Win’98 IRQ and PC-98/99 compliant
Supports parallel or serial interface for socket power
control including devices from Micrel and TI
Zoomed Video Support; Zoomed Video Buffer Enable
Pins
D3cold state PME# wakeup support
3.3Vaux Power Support
Integrated PC 98/99 -Subsystem Vendor ID support,
with auto lock bit
LED Activity Pins
ORDERING INFORMATION
OZ6933T – 208 pin TQFP
OZ6933B – 208 pin Mini-BGA
GENERAL DESCRIPTION
The OZ6933 is an ACPI and PC98/99 logo certified, high
performance, dual slot PC Card controller with a synchron-
ous 32-bit bus master/target PCI interface. This PC Card
to PCI bridge host controller is compliant with the 2000 PC
Card Standard. This standard incorporates the new 32-bit
OZ6933
ACPI CardBus Controller
CardBus while retaining the 16-bit PC Card specification as
defined by PCMCIA release 2.1. CardBus is intended to
support “temporal” add-in functions on PC Cards, such as
Memory cards, Network interfaces, FAX/Modems and other
wireless communication cards, etc. The high performance
and capability of the CardBus interface will enable the new
development of many new functions and applications.
The OZ6933 CardBus controller is compliant with the latest
ACPI-PCI Bus Power Management Interface Specification.
It supports all four power states and the PME# function for
maximum power savings and ACPI compliance. Additional
compliance to OnNow Power Management includes D3cold
state support, paving the way for low sleep state power
consumption and minimized resume times. To allow host
software to reduce power consumption further, the OZ6933
provides a power-down mode in which internal clock
distribution and the PC Card socket clocks are stopped. An
advanced CMOS process is also used to minimize system
power consumption.
The OZ6933 dual PCMCIA socket supports two 3.3V/5V
8/16-bit PC Card R2 cards or 32-bit CardBus R3 cards. The
R2 card support is compatible with the Intel 82365SL PCIC
controller, and the R3 card support is fully compliant with
the 2000 PC Card Standard CardBus specification. The
OZ6933 is a stand alone device, which means that it does
not require an additional buffer chip for the PC Card socket
interface. In addition, the OZ6933 supports dynamic PC
Card hot insertion and removal, with auto configuration
capabilities.
The OZ6933 is fully compliant with the 33Mhz PCI Bus
specification, v2.2. It supports a master device with intern-
al CardBus direct data transfer. The OZ6933 implements a
FIFO data buffer architecture between the PCI bus and
CardBus socket interface to enhance data transfers to
CardBus devices. The bi-directional FIFO buffer permits the
OZ6933 to accept data from a target bus (PCI or CardBus
interface) while simultaneously transferring data. This
architecture not only speeds up data transfers but also
prevents system deadlocks.
The OZ6933 is a PCMCIA R2/CardBus controller, providing
the most advanced design flexibility for PC Cards that inter-
face with advanced notebook designs.
07/20/00
Copyright 2000 by O2Micro
OZ6933-SF-1.7
All Rights Reserved
Page 1

1 page




OZ6933 pdf
OZ6933
PIN LIST
Bold Text = Normal Default Pin Name
PCI Bus Interface Pins
Pin Name
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
PERR#
Description
PCI Bus Address Input/Data: These
pins connect to PCI bus signals AD[31:0].
A Bus transaction consists of an address
phase followed by one or more data
phases.
PCI Bus Command/Byte Enable: The
command signaling and byte enables are
multiplexed on the same pins. During the
address phase of a transaction,
C/BE[3:0]# are interpreted as the bus
commands. During the data phase,
C/BE[3:0]# are interpreted as byte
enables. The byte enables are to be valid
for the entirety of each data phase, and
they indicate which bytes in the 32-bit data
path are to carry meaningful data for the
current data phase.
Cycle Frame: This input indicates to the
OZ6933 that a bus transaction is
beginning. While FRAME# is asserted,
data transfers continue. When FRAME#
is de-asserted, the transaction is in its final
phases.
Initiator Ready: This input indicates the
initiating agents ability to complete the
current data phase of the transaction.
IRDY# is used in conjunction with TRDY#.
Target Ready: This output indicates
target Agents the OZ6933s ability to
complete the current data phase of the
transaction. TRDY# is used in conjunction
with IRDY#.
Stop: This output indicates the current
target is requesting the master to stop the
current transaction.
Initialization Device Select: This input is
used as chip select during configuration
read and write transactions. This is a
point-to-point signal. IDSEL can be used
as a chip select during configuration read
and write transactions.
Device Select: This output is driven
active LOW when the PCI address is
recognized as supported, thereby acting
as the target for the current PCI cycle.
The Target must respond before timeout
occurs or the cycle will terminate.
Parity Error: The output is driven active
LOW when a data parity error is detected
during a write phase.
Pin Number
TQFP
BGA
4-5, 7-12, 16-
20, 22-24, 38-
43, 45-46, 48-
49, 51-56
E1, E2, F3, F1,
G5, H6, G3,
G2, H2, H1, J1,
J2, J3, J6, K1,
K2, M5, N2,
N1, N3, N6, P1,
P3, N5, P6, R2,
R3, T1, W4,
R6, U5, P7
13, 25, 36, 47 G1, K3, M3, R1
27 K6
29 L1
30 L2
32 L5
15 H5
31 L3
33 L6
Input
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-
Type
I/O
Power
Rail
4
Drive
PCI Spec
I/O 4
-
I/O 4
-
I/O 4
-
I/O 4 PCI Spec
I/O 4 PCI Spec
I4
-
I/O 4 PCI Spec
TO 4 PCI Spec
OZ6933-SF-1.7
Page 5

5 Page





OZ6933 arduino
OZ6933
Name1
Description2
Pin Number
Socket A
Socket B
Qty I/O
Pwr Drive
TQFP BGA TQFP BGA
BVD2/
-SPKR/
-LED/
CAUDIO
Battery Voltage Detect 2/Speaker/ 114 M14 190 C8 1
LED: In Memory Card Interface mode,
this input serves as the BVD2 (battery
warning status) input. In I/O Card
Interface mode, this input can be
configured as a cards -SPKR binary
audio input. For ATA or non-ATA
(SFF-68) disk-drive support, this input
can also be configured as a drive-
status LED input.
CardBus Audio: In CardBus mode,
this pin is the CAUDIO input.
I-PU
2 or 3
-
BVD1/
-STSCHG/
-RI/
CSTSCHG
Battery Voltage Detect 1/Status 118 N19 192
F8
1
I-PU
2 or 3
Change/Ring Indicate: In Memory
Card Interface mode, this input serves
as the BVD1 (battery-dead status)
input. In I/O Card Interface mode, this
input is the -STSCHG input, which
indicates to the OZ6933 that the cards
internal status has changed. If bit 7 of
the Interrupt and General Control
register is set to `1`, this pin serves as
the ring indicate input for wakeup-on-
ring system power management
support.
CardBus Status Change: In CardBus
mode, this pin is the CSTSCHG. This
pin can be used to generate PME#.
-
VS2/
CVS2
Voltage Sense 2: This pin is used in 104 W16 179 A10 1 I/O-PU
conjunction with VS1 to determine the
operating voltage of the card. This pin
is internally pulled high to the voltage
of the AuxVCC power pin under the
combined control of the external data
write bits and the CD pull up control
bits. This pin connects to PCMCIA
socket pin 57.
CardBus Voltage Sense: In CardBus
mode, these pins are the CVS2 pins.
1 CB-spec
VS1/
CVS1
Voltage Sense 1: This pin is used in 76
W10
152
E18
1 I/O-PU
conjunction with VS2 to determine the
operating voltage of the card. This pin
is internally pulled high to the voltage
of the AuxVCC power pin under the
combined control of the external data
write bits and the CD pull up control
bits. This pin connects to PCMCIA
socket pin 43.
CardBus Voltage Sense: In CardBus
mode, these pins are the CVS1 pins.
1 CB-spec
SOCKET_VCC Connect these pins to the Vcc supply 60,
R7, 200, E7, 2, 3 PWR
-
-
of the socket (pins 17 and 51 of the 198 R13 160, F13,
respective PCMCIA socket). These
143 G19
pins can be 0, 3.3, or 5 V, depending
on card presence, card type, and
system configuration. The socket
interface outputs (listed in this table,
Table 2-2) will operate at the voltage
applied to these pins, independent of
the voltage applied to other OZ6933
pin groups.
1To differentiate the sockets in the pin diagram, all socket- specific pins have either A_ or B_ prefixes to the pin names indicated.
For example, A_A[25:0] and B_A[25:0] are the independent address buses to the sockets.
2When a socket is configured as an ATA drive interface, socket interface pin functions change.
OZ6933-SF-1.7
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