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PDF OR3LP26B Data sheet ( Hoja de datos )

Número de pieza OR3LP26B
Descripción Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
Fabricantes Agere Systems 
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Data Sheet
March 2000
ORCA® OR3LP26B Field-Programmable System Chip (FPSC)
Embedded Master/Target PCI Interface
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of an FPGA-based design imple-
mentation, coupled with the high bandwidth of an
industry-standard PCI interface. The ORCA
OR3LP26B (a member of the Series 3+ FPSC family)
provides a full-featured 33/50/66 MHz, 32-/64-bit PCI
interface, fully designed and tested, in hardware, plus
FPGA logic for user-programmable functions.
PCI Bus Core Highlights
s Implemented in an ORCA Series 3 OR3L125B
base array, displacing the bottom ten rows of 28
columns.
s Core is a well-tested ASIC model.
s Fully compliant to Revision 2.2 of PCI Local Bus
specification.
s Operates at PCI bus speeds up to 66 MHz on a
32-/64-bit wide bus.
s Comprises two independent controllers for Master
and Target.
s Meets/exceeds all requirements for PICMG* Hot
Swap friendly silicon, full Hot Swap model, per the
CompactPCI* Hot Swap specification, PICMG 2.1
R1.0.
s PCI SIG Hot Plug (R1.0) compliant.
s Four internal FIFOs individually buffer both direc-
tions of both the Master and Target interfaces:
— Both Master FIFOs are 64 bits wide by 32 bits
deep.
— Both Target FIFOs are 64 bits wide by 16 bits
deep.
s Capable of no-wait-state, full-burst PCI transfers in
either direction, on either the Master or Target
interface. The dual 64-bit data paths extend into
the FPGA logic, permitting full-bandwidth, simulta-
neous bidirectional data transfers of up to
528 Mbytes/s to be sustained indefinitely.
s Can be configured to provide either two 64-bit
buses (one in each direction) to be multiplexed
between Master and Target, or four independent
32-bit buses.
s Provides many hardware options in the PCI core
that are set during FPGA logic configuration.
s Operates within the requirements of the PCI 5 V
and 3.3 V signaling environments and 3.3 V com-
mercial environmental conditions, allowing the
same device to be used in 5 V or 3.3 V PCI sys-
tems.
s FPGA is reconfigurable via the PCI interface's con-
figuration space (as well as conventionally), allow-
ing the FPGA to be field-updated to meet late-
breaking requirements of emerging protocols.
* PICMG and CompactPCI are registered trademarks of the PCI
Industrial Computer Manufacturers Group.
Table 1. ORCA OR3LP26B PCI FPSC Solution—Available FPGA Logic
Device
OR3LP26B
Usable Gates
Number of
LUTs
Number of
Registers
Max User
RAM
Max User
I/Os
60K—120K
4032
5304
64K
259
Array
Size
18 x 28
Number of
PFUs
504
† The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable
gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only
gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12
gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic,
CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4
RAM (or 512 gates) per PFU.

1 page




OR3LP26B pdf
Data Sheet
March 2000
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Highlights (continued)
s Master:
— Generates all defined command codes except
interrupt acknowledge and special cycle.
— Capable of accessing its own local Target.
— Capable of acting as the system's configuration
agent by booting up with the Master logic
enabled.
— Supports multiple options for Master bus requests,
to increase PCI bus bandwidth.
— Supports single-cycle I/O space accesses.
— Provides option to delay PCI access until FIFO is
full on Master writes to increase PCI bandwidth.
— Supports programmable latency timer control.
s Target:
— Responds legally to all command codes: interrupt
acknowledge, special cycle, and reserved com-
mands ignored; memory read multiple and line
handled as memory read; memory write and
invalidate handled as memory write.
— Implements Target abort, disconnect, retry, and
wait cycles.
— Handles delayed transactions.
— Handles fast back-to-back transactions.
— Method of handling retries is programmable at
FPGA configuration to allow tailoring to different
Target data access latencies.
— Decodes at medium speed.
— Provides option to delay PCI access until FIFO is
full on Target reads to increase PCI bandwidth.
s Supports dual-address cycles (both as Master and
Target).
s Supports all six base address registers (BARs), as
either memory (32-bit or 64-bit) or I/O. Any legal
page size can be independently specified for each
BAR during FPGA configuration.
s Independent Master and Target clocks can be sup-
plied to the PCI FIFO interface from the FPGA-based
logic.
s Provides versatile clocking capabilities with FPGA
clocks sourced from PCI bus clock or elsewhere.
FIFO interface buffers asynchronous clock domains
between the PCI interface and FPGA-based logic.
s PCI interface timing: meets or exceeds 33 MHz,
50 MHz, and 66 MHz PCI requirements.
Parameter
Device Clock = > Out
Device Setup Time
Board Prop. Delay
Board Clock Skew
Total Budget
Load Capacitance
33 MHz
11.0 ns
7.0 ns
10.0 ns
2.0 ns
30.0 ns
50 pF
50 MHz
7.5 ns
4.5 ns
6.5 ns
1.5 ns
20.0 ns
50 pF
66 MHz
6.0 ns
3.0 ns
5.0 ns
1.0 ns
15.0 ns
10 pF
s Configuration options:
— Class code, revision ID.
— Latency timer.
— Cache line size.
— Subsystem ID.
— Subsystem vendor ID.
— Maximum latency, minimum grant.
— Interrupt line.
— Hot Plug/Hot Swap capability.
s Generates interrupts on intan as directed by the
FPGA.
s PCI I/O output drivers can be programmed for fast or
slew-limited operation.
s Automatically detects 5 V or 3.3 V PCI bus signaling
environment and provides appropriate I/O signaling,
under 3.3 V commercial conditions.
s Ideally suited for such applications as:
— PCI-based graphics/video/multimedia.
— Bridges to ISA/EISA/MCA, LAN, SCSI, Ethernet,
ATM, or other bus architectures.
— High-bandwidth data transfer in proprietary sys-
tems.
FPSC Highlights
s Implemented as an embedded core into the
advanced Series 3+ ORCA FPSC architecture.
s Allows the user to integrate the core with up to 120K
gates of programmable logic, all in one device, and
provides up to 259 user I/O pins in addition to the
PCI interface pins.
s FPGA portion retains all of the features of the ORCA
3 FPGA architecture:
— High-performance, cost-effective, 0.25 µm
5-level metal technology.
— Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables
(LUTs) per PFU, organized in two nibbles for use
in nibble- or byte-wide functions. Allows for mixed
arithmetic and logic functions in a single PFU.
Lucent Technologies Inc.
Lucent Technologies Inc.
5

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OR3LP26B arduino
Data Sheet
March 2000
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
OR3LP26B Overview (continued)
Table 3. OR3LP26B Array
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PT8
PT9
PT10
PT11
PT12
PT13
PT14
R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R1
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R4 R4 R4 R4 R4 R4 R4 R4 R4 R4 R4 R4 R4 R4
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R5 R5 R5 R5 R5 R5 R5 R5 R5 R5 R5 R5 R5 R5
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R6 R6 R6 R6 R6 R6 R6 R6 R6 R6 R6 R6 R6 R6
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R7 R7 R7 R7 R7 R7 R7 R7 R7 R7 R7 R7 R7 R7
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R8 R8 R8 R8 R8 R8 R8 R8 R8 R8 R8 R8 R8 R8
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R9 R9 R9 R9 R9 R9 R9 R9 R9 R9 R9 R9 R9 R9
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R10 R10 R10 R10 R10 R10 R10 R10 R10 R10 R10 R10 R10 R10
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R11 R11 R11 R11 R11 R11 R11 R11 R11 R11 R11 R11 R11 R11
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R12 R12 R12 R12 R12 R12 R12 R12 R12 R12 R12 R12 R12 R12
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R13 R13 R13 R13 R13 R13 R13 R13 R13 R13 R13 R13 R13 R13
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R14 R14 R14 R14 R14 R14 R14 R14 R14 R14 R14 R14 R14 R14
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PT15
R1
C15
R2
C15
R3
C15
R4
C15
R5
C15
R6
C15
R7
C15
R8
C15
R9
C15
R10
C15
R11
C15
R12
C15
R13
C15
R14
C15
PT16
R1
C16
R2
C16
R3
C16
R4
C16
R5
C16
R6
C16
R7
C16
R8
C16
R9
C16
R10
C16
R11
C16
R12
C16
R13
C16
R14
C16
PT17
R1
C17
R2
C17
R3
C17
R4
C17
R5
C17
R6
C17
R7
C17
R8
C17
R9
C17
R10
C17
R11
C17
R12
C17
R13
C17
R14
C17
PT18
R1
C18
R2
C18
R3
C18
R4
C18
R5
C18
R6
C18
R7
C18
R8
C18
R9
C18
R10
C18
R11
C18
R12
C18
R13
C18
R14
C18
PT19
R1
C19
R2
C19
R3
C19
R4
C19
R5
C19
R6
C19
R7
C19
R8
C19
R9
C19
R10
C19
R11
C19
R12
C19
R13
C19
R14
C19
PT20
R1
C20
R2
C20
R3
C20
R4
C20
R5
C20
R6
C20
R7
C20
R8
C20
R9
C20
R10
C20
R11
C20
R12
C20
R13
C20
R14
C20
PT21
R1
C21
R2
C21
R3
C21
R4
C21
R5
C21
R6
C21
R7
C21
R8
C21
R9
C21
R10
C21
R11
C21
R12
C21
R13
C21
R14
C21
PT22
R1
C22
R2
C22
R3
C22
R4
C22
R5
C22
R6
C22
R7
C22
R8
C22
R9
C22
R10
C22
R11
C22
R12
C22
R13
C22
R14
C22
PT23
R1
C23
R2
C23
R3
C23
R4
C23
R5
C23
R6
C23
R7
C23
R8
C23
R9
C23
R10
C23
R11
C23
R12
C23
R13
C23
R14
C23
PT24
R1
C24
R2
C24
R3
C24
R4
C24
R5
C24
R6
C24
R7
C24
R8
C24
R9
C24
R10
C24
R11
C24
R12
C24
R13
C24
R14
C24
PT25
R1
C25
R2
C25
R3
C25
R4
C25
R5
C25
R6
C25
R7
C25
R8
C25
R9
C25
R10
C25
R11
C25
R12
C25
R13
C25
R14
C25
PT26
R1
C26
R2
C26
R3
C26
R4
C26
R5
C26
R6
C26
R7
C26
R8
C26
R9
C26
R10
C26
R11
C26
R12
C26
R13
C26
R14
C26
PT27
R1
C27
R2
C27
R3
C27
R4
C27
R5
C27
R6
C27
R7
C27
R8
C27
R9
C27
R10
C27
R11
C27
R12
C27
R13
C27
R14
C27
PT28
R1
C28
R2
C28
R3
C28
R4
C28
R5
C28
R6
C28
R7
C28
R8
C28
R9
C28
R10
C28
R11
C28
R12
C28
R13
C28
R14
C28
R15 R15 R15 R15 R15 R15 R15 R15 R15 R15 R15 R15 R15 R15
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R16 R16 R16 R16 R16 R16 R16 R16 R16 R16 R16 R16 R16 R16
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R17 R17 R17 R17 R17 R17 R17 R17 R17 R17 R17 R17 R17 R17
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
R18
C1
ASB1
R18
C2
ASB2
R18
C3
ASB3
R18
C4
ASB4
R18
C5
ASB5
R18
C6
ASB6
R18
C7
ASB7
R18
C8
ASB8
R18
C9
ASB9
R18 R18 R18 R18 R18
C10 C11 C12 C13 C14
ASB10 ASB11 ASB12 ASB13 ASB14
R15 R15 R15 R15 R15 R15 R15 R15 R15 R15 R15 R15 R15 R15
C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28
R16 R16 R16 R16 R16 R16 R16 R16 R16 R16 R16 R16 R16 R16
C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28
R17 R17 R17 R17 R17 R17 R17 R17 R17 R17 R17 R17 R17 R17
C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28
R18 R18 R18 R18 R18 R18 R18 R18 R18 R18 R18 R18 R18 R18
C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28
ASB15 ASB16 ASB17 ASB18 ASB19 ASB20 ASB21 ASB22 ASB23 ASB24 ASB25 ASB26 ASB27 ASB28
EMBEDDED CORE AREA
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII III IIII IIII IIII IIII
Lucent Technologies Inc.
Lucent Technologies Inc.
11

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