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PDF OPA847 Data sheet ( Hoja de datos )

Número de pieza OPA847
Descripción Wideband / Ultra-Low Noise / Voltage-Feedback
Fabricantes Burr-Brown 
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No Preview Available ! OPA847 Hoja de datos, Descripción, Manual

OPA847
OPA847
SBOS251C – JULY 2002 – REVISED OCTOBER 2003
Wideband, Ultra-Low Noise, Voltage-Feedback
OPERATIONAL AMPLIFIER with Shutdown
FEATURES
z HIGH GAIN BANDWIDTH: 3.9GHz
z LOW INPUT VOLTAGE NOISE: 0.85nV/Hz
z VERY LOW DISTORTION: –105dBc (5MHz)
z HIGH SLEW RATE: 950V/µs
z HIGH DC ACCURACY: VIO < ±100µV
z LOW SUPPLY CURRENT: 18.1mA
z LOW SHUTDOWN POWER: 2mW
z STABLE FOR GAINS 12
APPLICATIONS
z HIGH DYNAMIC RANGE ADC PREAMPS
z LOW NOISE, WIDEBAND, TRANSIMPEDANCE
AMPLIFIERS
z WIDEBAND, HIGH GAIN AMPLIFIERS
z LOW NOISE DIFFERENTIAL RECEIVERS
z ULTRASOUND CHANNEL AMPLIFIERS
z IMPROVED UPGRADE FOR THE OPA687,
CLC425, AND LMH6624
50Source
1:2
< 5.1dB
Noise
Figure
100
39pF
39pF
100
+5V
OPA847
1.7pF
–5V
850
850
+5V
1.7pF
OPA847
0.001µF
20
+5V
2k
VIN+
100pF
VCM
ADS5421
14-Bit
0.1µF
40MSPS
2k
0.001µF 20
VIN
100pF
–5V 24.6dB Gain
Ultra-High Dynamic Range
Differential ADC Driver
DESCRIPTION
The OPA847 combines very high gain bandwidth and large
signal performance with an ultra-low input noise voltage
(0.85nV/Hz) while using only 18mA supply current. Where
power savings is critical, the OPA847 also includes an
optional power shutdown pin that, when pulled low, disables
the amplifier and decreases the supply current to < 1% of the
powered-up value. This optional feature may be left discon-
nected to ensure normal amplifier operation when no power-
down is required.
The combination of very low input voltage and current noise,
along with a 3.9GHz gain bandwidth product, make the
OPA847 an ideal amplifier for wideband transimpedance
applications. As a voltage gain stage, the OPA847 is opti-
mized for a flat frequency response at a gain of +20V/V and
is stable down to gains as low as +12V/V. New external
compensation techniques allow the OPA847 to be used at
any inverting gain with excellent frequency response control.
Using this technique in a differential Analog-to-Digital Con-
verter (ADC) interface application, shown below, can deliver
one of the highest dynamic-range interfaces available.
OPA847 RELATED PRODUCTS
SINGLES
OPA842
OPA843
OPA846
INPUT NOISE
VOLTAGE (nV/Hz )
2.6
2.0
1.2
GAIN BANDWIDTH
PRODUCT (MHz)
200
800
1750
DIFFERENTIAL OPA847 DRIVER DISTORTION
–70
2VPP, at converter input.
–75
–80
–85
–90
–95
–100
2nd-Harmonic
3rd-Harmonic
–105
–110
10
20 30
Frequency (MHz)
40 50
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2002-2003, Texas Instruments Incorporated

1 page




OPA847 pdf
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = 25°C, G = +20V/V, RG = 39.2, and RL = 100, unless otherwise noted.
5MHz HARMONIC DISTORTION vs LOAD RESISTANCE
–70
G = +20V/V
–75 VO = 2VPP
–80
–85
–90
2nd-Harmonic
–95
–100
–105
3rd-Harmonic
–110
See Figure 1
–115
100 150 200 250 300 350 400 450 500
Load Resistance ()
1MHz HARMONIC DISTORTION vs LOAD RESISTANCE
–75
G = +20V/V
VO = 5VPP
–80
2nd-Harmonic
–85
–90
–95
3rd-Harmonic
–100
See Figure 1
–105
100 150 200 250 300 350 400 450 500
Load Resistance ()
HARMONIC DISTORTION vs FREQUENCY
–65
G = +20V/V
VO = 2VPP
–75 RL = 200
2nd-Harmonic
–85
–95
–105
See Figure 1
–115
0.1
3rd-Harmonic
1 10
Frequency (MHz)
100
HARMONIC DISTORTION vs OUTPUT VOLTAGE
–75 G = +20V/V
–80 F = 5MHz
RL = 200
–85
2nd-Harmonic
–90
–95
–100
–105
3rd-Harmonic
–110
See Figure 1
–115
0.1
1
Output Voltage Swing (VPP)
10
HARMONIC DISTORTION vs NONINVERTING GAIN
–75
–80
–85
–90
–95
–100
VO = 2VPP
RL = 200
F = 5MHz
RF = 750
RG Adjusted
–105
–110
15 20 25
2nd-Harmonic
3rd-Harmonic
30 35 40 45
Gain (V/V)
See Figure 1
50 55 50
HARMONIC DISTORTION vs INVERTING GAIN
–70
–75
–80
2nd-Harmonic
–85
–90
–95
–100
VO = 2VPP
RL = 200
F = 5MHz
RG = 50
RF Adjusted
–105
–110
20
25
30
3rd-Harmonic
See Figure 2
35 40 45 50
Gain –V/V
OPA847
SBOS251C
www.ti.com
5

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OPA847 arduino
The high GBP and low input voltage and current noise for the
OPA847 make it an ideal wideband transimpedance ampli-
fier for low to moderate transimpedance gains. Very high
transimpedance gains (> 100k) will benefit from the low
input noise current of a JFET input op amp such as the
OPA657. Unity-gain stability in the op amp is not required for
application as a transimpedance amplifier. Figure 3 shows
one possible transimpedance design example that would be
particularly suitable for the 155Mbit data rate of an OC-3
receiver. Designs that require high bandwidth from a large
area detector with relatively low transimpedance gain will
benefit from the low input voltage noise for the OPA847. The
amplifier’s input voltage noise is peaked up over frequency
by the diode source capacitance, and can (in many cases)
become the limiting factor to input sensitivity. The key ele-
ments to the design are the expected diode capacitance (CD)
with the reverse bias voltage (–VB) applied, the desired
transimpedance gain (RF), and the GBP for the OPA847
(3900MHz). With these three variables set (including the
parasitic input capacitance for the OPA847 added to CD), the
feedback capacitor value (CF) can be set to control the
frequency response.
To achieve a maximally flat 2nd-order Butterworth frequency
response, set the feedback pole as shown in Equation 1.
100pF
+5V
Power-supply
decoupling not shown.
0.1µF 12kOPA847
VDIS
–5V
RF
12k
λ
1pF
Photodiode
CF
0.18pF
–VB
FIGURE 3. Wideband, High Sensitivity, OC-3 Transimpedance
Amplifier.
1 GBP
2πRF CF = 4πRF CD
(1)
Adding the common-mode and differential mode input ca-
pacitance (1.2 + 2.5)pF to the 1pF diode source capacitance
of Figure 3, and targeting a 12ktransimpedance gain
using the 3900MHz GBP for the OPA847 requires a feed-
back pole set to 74MHz to get a nominal Butterworth fre-
quency response design. This requires a total feedback
capacitance of 0.18pF. That total is shown in Figure 3, but
recall that typical surface-mount resistors have a parasitic
capacitance of 0.2pF, leaving no external capacitor required
for this design.
Equation 2 gives the approximate –3dB bandwidth that
results if CF is set using Equation 1.
f 3 dB =
GBP (Hz )
2πRF CD
(2)
The example of Figure 3 gives approximately 104MHz flat
bandwidth using the 0.18pF feedback compensation capaci-
tor. This bandwidth easily supports an OC-3 receiver with
exceptional sensitivity.
If the total output noise is bandlimited to a frequency less
than the feedback pole frequency, a very simple expression
for the equivalent input noise current is shown as Equation 3.
( )iEQ=
iN2 +
4kT
RF
+
eN
RF
 2 +
eN2πCD F
3
2
(3)
where:
iEQ = Equivalent input noise current if the output noise is
bandlimited to F < 1/(2πRFCF)
iN = Input current noise for the op amp inverting input
eN = Input voltage noise for the op amp
CD = Total Inverting Node Capacitance
f = Bandlimiting frequency in Hz (usually a post filter prior
to further signal processing)
Evaluating this expression up to the feedback pole fre-
quency at 74MHz for the circuit of Figure 3 gives an equiva-
lent input noise current of 3.0pA/Hz. This is slightly higher
than the 2.5pA/Hz input current noise for the op amp. This
total equivalent input current noise is slightly increased by
the last term in the equivalent input noise expression. It is
essential in this case to use a low-voltage noise op amp. For
example, if a slightly higher input noise voltage, but other-
wise identical, op amp were used instead of the OPA847 in
this application (say 2.0nV/Hz), the total input referred
current noise would increase to 3.7pA/Hz. Low input volt-
age noise is required for the best sensitivity in these wideband
transimpedance applications. This is often unspecified for
dedicated transimpedance amplifiers with a total output
noise for a specified source capacitance given instead. It is
the relatively high input voltage noise for those components
that cause higher than expected output noise if the source
capacitance is higher than specified.
The output DC error for the circuit of Figure 3 is minimized
by including a 12kto ground on the noninverting input.
This reduces the contribution of input bias current errors (for
total output offset voltage) to the offset current times the
feedback resistor. To minimize the output noise contribution
of this resistor, 0.01µF and 100pF capacitors are included in
parallel. Worst-case output DC error for the circuit of Figure
3 at 25°C is:
Vos = ±0.5mV (input offset voltage) ± 0.6uA (input offset
current) • 12k= ±7.2mV
Worst-case output offset DC drift (over the 0°C to 70°C span) is:
dVos/dT = ±1.5µV/°C (input offset drift) ± 2nA/°C (input
offset current drift) • 12k= ±21.5µV/°C.
OPA847
SBOS251C
www.ti.com
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