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PDF OP467 Data sheet ( Hoja de datos )
| Número de pieza | OP467 | |
| Descripción | Quad Precision / High Speed Operational Amplifier | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
High Slew Rate – 170 V/s
Wide Bandwidth – 28 MHz
Fast Settling Time – <200 ns to 0.01%
Low Offset Voltage – <500 V
Unity-Gain Stable
Low Voltage Operation ؎5 V to ؎15 V
Low Supply Current – <10 mA
Drives Capacitive Loads
APPLICATIONS
High Speed Image Display Drivers
High Frequency Active Filters
Fast Instrumentation Amplifiers
High Speed Detectors
Integrators
Photo Diode Preamps
GENERAL DESCRIPTION
The OP467 is a quad, high speed, precision operational ampli-
fier. It offers the performance of a high speed op amp combined
with the advantages of a precision operational amplifier all in a
single package. The OP467 is an ideal choice for applications
where, traditionally, more than one op amp was used to achieve
this level of speed and precision.
The OP467’s internal compensation ensures stable unity-gain
operation, and it can drive large capacitive loads without oscilla-
tion. With a gain bandwidth product of 28 MHz driving a 30 pF
load, output slew rate in excess of 170 V/µs, and settling time to
0.01% in less than 200 ns, the OP467 provides excellent dy-
namic accuracy in high speed data-acquisition systems. The
channel-to-channel separation is typically 60 dB at 10 MHz.
The dc performance of OP467 includes less than 0.5 mV of
offset, voltage noise density below 6 nV/√Hz and total supply
current under 10 mA. Common-mode rejection and power
supply rejection ratios are typically 85 dB. PSRR is maintained
to better than 40 dB with input frequencies as high as 1 MHz.
The low offset and drift plus high speed and low noise, make the
OP467 usable in applications such as high speed detectors and
instrumentation.
The OP467 is specified for operation from ± 5 V to ± 15 V over
the extended industrial temperature range (–40°C to +85°C) and
is available in 14-lead plastic and ceramic DIP, plus SOL-16
and 20-lead LCC surface mount packages.
Contact your local sales office for MIL-STD-883 data sheet and
availability.
Quad Precision, High Speed
Operational Amplifier
OP467
PIN CONNECTIONS
14-Lead Ceramic DIP (Y Suffix) and
14-Lead Epoxy DIP (P Suffix)
OUT A 1
–IN A 2
+IN A 3
V+ 4
+IN B 5
–IN B 6
OUT B 7
++
OP467
++
14 OUT D
13 –IN D
12 +IN D
11 V–
10 +IN C
9 –IN C
8 OUT C
16-Lead SOL
(S Suffix)
OUT A 1
16 OUT D
–IN A 2
15 –IN D
+IN A 3
14 +IN D
V+ 4 OP467 13 V–
+IN B 5
12 +IN C
–IN B 6
11 –IN C
OUT B 7
10 OUT C
NC 8
9 NC
NC = NO CONNECT
20-Position Chip Carrier
(RC Suffix)
3 2 1 20 19
+IN A 4
NC 5
V+ 6
NC 7
+IN B 8
OP467
(TOP VIEW)
18 +IN D
17 NC
16 V–
15 NC
14 +IN C
9 10 11 12 13
NC = NO CONNECT
V+
+IN OUT
–IN
V–
Figure 1. Simplified Schematic
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
Typical Performance Characteristics–OP467
80
VS = ؎15V
70 RL = 1M⍀
60 CL = 30pF
GAIN
50
40
30
PHASE
20
0
10 90
0 180
–10
–20
1k
10k 100k 1M
10M 100M
FREQUENCY – Hz
Figure 2. Open-Loop Gain, Phase vs. Frequency
100
VS = ؎15V
TA = +25؇C
80
60
AVCL = +100
40
AVCL = +10
20
AVCL = +1
0
100 1k 10k 100k 1M
FREQUENCY – Hz
Figure 5. Closed-Loop Output Impedance vs. Frequency
80
VS = ؎15V
TA = +25؇C
60
40
20
0
–20
10k
100k
1M
FREQUENCY – Hz
10M
100M
Figure 3. Closed-Loop Gain vs. Frequency
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
VS = ؎5
VS = ؎15
100k
1M
FREQUENCY – Hz
3.4 5.8 10M
Figure 6. Gain Linearity vs. Frequency
25
20
15
TA = +125؇C
TA = +25؇C
10
TA = –55؇C
5
0
0 ؎5 ؎10 ؎15 ؎20
SUPPLY VOLTAGE – Volts
Figure 4. Open-Loop Gain vs. Supply Voltage
30
AVCL = –1
25
AVCL = +1
20
15
10
VS = ؎15V
5 TA = +25؇C
RL = 2k⍀
0
1k 10k 100k 1M 10M
FREQUENCY – Hz
Figure 7. Max VOUT Swing vs. Frequency
REV. C
–5–
5 Page 
OP467
APPLICATIONS INFORMATION
OUTPUT SHORT-CIRCUIT PERFORMANCE
To achieve a wide bandwidth and high slew rate, the OP467
output is not short circuit protected. Shorting the output to
ground or to the supplies may destroy the device.
For safe operation, the output load current should be limited so
that the junction temperature does not exceed the absolute
maximum junction temperature.
To calculate the maximum internal power dissipation, the fol-
lowing formula can be used:
PD
= TJ
max– TA
θJA
where TJ and TA are junction and ambient temperatures respec-
tively, PD is device internal power dissipation, and θJA is pack-
aged device thermal resistance given in the data sheet.
UNUSED AMPLIFIERS
It is recommended that any unused amplifiers in a quad package
be connected as a unity gain follower with a 1 kΩ feedback
resistor with noninverting input tied to the ground plain.
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Satisfactory performance of a high speed op amp largely depends
on a good PC layout. To achieve the best dynamic performance,
following high frequency layout technique is recommended.
GROUNDING
A good ground plain is essential to achieve the optimum perfor-
mance in high speed applications. It can significantly reduce the
undesirable effects of ground loops and IR drops by providing a
low impedance reference point. Best results are obtained with a
multilayer board design with one layer assigned to ground plain.
To maintain a continuous and low impedance ground, avoid
running any traces on this layer.
POWER SUPPLY CONSIDERATIONS
In high frequency circuits, device lead length introduces an
inductance in series with the circuit. This inductance, combined
with stray capacitance, forms a high frequency resonance circuit.
Poles generated by these circuits will cause gain peaking and
additional phase shift, reducing the op amp’s phase margin and
leading to an unstable operation.
A practical solution to this problem is to reduce the resonance
frequency low enough to take advantage of the amplifier’s power
supply rejection.
This is easily done by placing capacitors across the supply line
and the ground plain as close as possible to the device pin. Since
capacitors also have internal parasitic components, such as stray
inductance, selecting the right capacitor is important. To be
effective, they should have low impedance over the frequency
range of interest. Tantalum capacitors are an excellent choice
for their high capacitance/size ratio, but their ESR (Effective
Series Resistance) increases with frequency making them less
effective. On the other hand, ceramic chip capacitors have excel-
lent ESR and ESL (Effective Series Inductance) performance at
higher frequencies, and because of their small size, they can be
placed very close to the device pin, further reducing the stray
inductance. Best results are achieved by using a combination of
these two capacitors. A 5 µF–10 µF tantalum parallel with a
0.1 µF ceramic chip caps are recommended. If additional isola-
tion from high frequency resonances of the power supply is
needed, a ferrite bead should be placed in series with the supply
lines between the bypass caps and the power supply. A word of
caution, addition of the ferrite bead will introduce a new pole
and zero to frequency response of the circuit and could cause
unstable operation if it is not selected properly.
+VS
+
10F TANTALUM
0.1F CERAMIC CHIP
0.1F CERAMIC CHIP
– 10F TANTALUM
–VS
Figure 36. Recommended Power Supply Bypass
SIGNAL CONSIDERATIONS
Input and output traces need special attention to assure a mini-
mum stray capacitance. Input nodes are very sensitive to capaci-
tive reactance, particularly when connected to a high impedance
circuit. Stray capacitance can inject undesirable signals from a
noisy line into a high impedance input. Protect high impedance
input traces by providing guard traces around them. This will
also improve the channel separation significantly.
Additionally, any stray capacitance in parallel with the op amp’s
input capacitance generates a pole in the frequency response of
the circuit. The additional phase shift caused by this pole will
reduce the circuit’s gain margin. If this pole is within the gain
range of the op amp, it will cause unstable performance. To
reduce these undesirable effects, use the lowest impedance
where possible. Lowering the impedance at this node places the
poles at a higher frequency, far above the gain range of the am-
plifier. Stray capacitance on the PC board can be reduced by
making the traces narrow and as short as possible. Further re-
duction can be realized by choosing smaller pad size, increasing
the spacing between the traces, and using PC board material
with a low dielectric constant insulator (Dielectric Constant of
some common insulators: air = 1, Teflon® = 2.2, and FR4 =
4.7; with air being an ideal insulator).
Removing segments of the ground plain directly under the input
and output pads is recommended.
Outputs of high speed amplifiers are very sensitive to capacitive
loads. A capacitive load will introduce a pair of pole and zero to
the circuit’s frequency response, reducing the phase margin,
leading to unstable operation or oscillation.
Teflon is a registered trademark of E.I. du Pont Co.
REV. C
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet OP467.PDF ] | |
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