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PDF OM6206Z Data sheet ( Hoja de datos )

Número de pieza OM6206Z
Descripción 65 X 102 pixels matrix LCD driver
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! OM6206Z Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
OM6206
65 × 102 pixels matrix LCD driver
Product specification
File under Integrated Circuits, IC17
2001 Nov 14

1 page




OM6206Z pdf
Philips Semiconductors
65 × 102 pixels matrix LCD driver
Product specification
OM6206
6 PINNING
SYMBOL
R0 to R18
R19 to R32
R33 to R50
R51 to R64
C0 to C101
VSS1
VSS2
VDD1
VDD2
VDD3
VLCDIN
VLCDOUT
VLCDSENSE
T1
T2
T3
T4
T5
SCLK
SDIN
D/C
SCE
OSC
RES
PAD
18 to 36
2 to 15
156 to 139
159 to 172
37 to 138
214 to 217,
221 and 222
200 to 213
174 to 179
181 to 193
180
224 to 229
230 to 236
237
218
198
223
220
219
194
195
196
197
199
1
DESCRIPTION
LCD row driver outputs
LCD row driver outputs
LCD row driver outputs
LCD row driver outputs
LCD column driver outputs
ground supply 1
ground supply 2
supply voltage 1
supply voltage 2
supply voltage 3
LCD supply voltage (VLCD)
voltage multiplier output
(VLCD)
voltage multiplier
regulation input (VLCD)
test 1 input
test 2 output
test 3 input/output
test 4 input
test 5 input
serial clock input
serial data input
data or command selection
input
chip enable (active LOW)
oscillator signal input
external reset input (active
LOW)
6.1 Pin functions
6.1.1 R0 TO R64: ROW DRIVER OUTPUTS
These pins output the row signals.
6.1.2 C0 TO C101: COLUMN DRIVER OUTPUTS
These pins output the column signals.
6.1.3 VSS1 AND VSS2: GROUND SUPPLY RAILS
The supply rails VSS1 and VSS2 must be connected
together.
6.1.4 VDD1, VDD2 AND VDD3: SUPPLY VOLTAGE RAILS
VDD2 and VDD3 are the supply voltage for the internal
voltage generator. Both have the same voltage and should
be connected together outside the chip. VDD1 is used as
supply voltage for the rest of the chip. VDD1 can be
connected together with VDD2 and VDD3 but in this case
care must be taken to respect the supply voltage range
(see Chapter 11).
If the internal voltage generator is not used the pins
VDD2 and VDD3 must be connected to pin VDD1 or
connected to the supply voltage.
6.1.5 VLCDIN: LCD SUPPLY VOLTAGE
Positive supply voltage for the liquid crystal display. An
external LCD supply voltage can be supplied using
pin VLCDIN. In this case, VLCDOUT has to be left open and
the internal voltage generator has to be programmed to
zero. If the OM6206 is in Power-down mode, the external
LCD supply voltage has to be switched off.
6.1.6 VLCDOUT: VOLTAGE MULTIPLIER OUTPUT
Positive supply voltage for the liquid crystal display. If the
internal voltage generator is used, the two supply rails
VLCDIN and VLCDOUT must be connected together. If an
external supply is used this pin must be left open.
6.1.7
VLCDSENSE: VOLTAGE MULTIPLIER REGULATION
INPUT
VLCDSENSE is the input of the internal voltage multiplier
regulation.
If the internal voltage generator is used then VLCDSENSE
must be connected to VLCDOUT. If an external supply
voltage is used then VLCDSENSE can be left open or
connected to ground.
6.1.8 T1 TO T5: TEST PINS
T1, T3, T4 and T5 must be connected to VSS, T2 must be
left open. Not accessible to user.
2001 Nov 14
5

5 Page





OM6206Z arduino
Philips Semiconductors
65 × 102 pixels matrix LCD driver
Product specification
OM6206
handbook, halfpMagSeB (DB7)
data
LSB (DB0)
data
MGT865
Fig.7 General format of data stream.
handbook, full pagewidth
function set (H = 1)
bias system
set VOP
temperature control
function set (H = 0) display control
Y-address
Fig.8 Serial data stream, example.
X-address
MGT866
Figures 9 and 10 show the serial bus protocol:
When SCE is HIGH, SCLK clock signals are ignored.
During the HIGH time of SCE, the serial interface is
initialized (see Fig.11)
SDIN is sampled at the positive edge of SCLK
D/C indicates, whether the byte is a command
(D/C = LOW) or RAM data (D/C = HIGH); it is read with
the eighth SCLK pulse
If SCE stays LOW after the last bit of a
command/data byte, the serial interface expects bit 7 of
the next byte at the next positive edge of SCLK (see
Fig.11)
A reset pulse with RES interrupts the transmission.
No data are written into the RAM. The registers are
cleared. If SCE is LOW after the positive edge of RES,
the serial interface is ready to receive bit 7 of a
command/data byte (see Fig.11).
handbook, full pageSwCidEth
D/ C
SCLK
SDIN
2001 Nov 14
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Fig.9 Serial bus protocol for transmission of one byte.
MGT867
11

11 Page







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