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PDF NDS356AP Data sheet ( Hoja de datos )

Número de pieza NDS356AP
Descripción P-Channel Logic Level Enhancement Mode Field Effect Transistor
Fabricantes Fairchild 
Logotipo Fairchild Logotipo



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September 1996
NDS356AP
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOTTM-3 P-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications such as notebook computer power management,
portable electronics, and other battery powered circuits where
fast high-side switching, and low in-line power loss are
needed in a very small outline surface mount package.
Features
-1.1 A, -30 V, RDS(ON) = 0.3 @ VGS=-4.5 V
RDS(ON) = 0.2 @ VGS=-10 V.
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
________________________________________________________________________________
D
Absolute Maximum Ratings
Symbol Parameter
TA = 25°C unless otherwise noted
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID
Maximum Drain Current - Continuous
(Note 1a)
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient (Note 1a)
Thermal Resistance, Junction-to-Case
(Note 1)
GS
NDS356AP
-30
±20
±1.1
±10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS356AP Rev.C1

1 page




NDS356AP pdf
Typical Electrical Characteristics (continued)
1.08
1.06
ID = -250µA
1.04
1.02
1
0.98
0.96
0.94
-50
-25
0 25 50 75 100 125 150
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage Variation with
Temperature.
5
2 VGS = 0V
1
0.5
0.1
0.01
0.001
TJ = 125°C
25°C
-55°C
0.0001
0
0.2 0.4 0.6 0.8
1
-VSD , BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature.
600
400
300 Ciss
200 Coss
100
Crss
f = 1 MHz
50 VGS = 0 V
30
0.1
0.2
0.5 1
2
5 10
-V , DRAIN TO SOURCE VOLTAGE (V)
DS
20
Figure 9. Capacitance Characteristics.
10
ID = -1.1A
8
6
VDS= -5V
-15V
-10V
4
2
0
01234567
Q g , GATE CHARGE (nC)
Figure 10. Gate Charge Characteristics.
VIN
VGS
RGEN
G
VDD
RL
D
V OUT
DUT
S
t d(on)
ton
tr
90%
td(off)
toff
tf
90%
VO U T
VIN
10%
10%
50%
10%
90%
50%
PULSE WIDTH
INVERTED
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
NDS356AP Rev.C1

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