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Número de pieza NCP1010
Descripción Self-Supplied Monolithic Switcher for Low Standby- Power Offline SMPS
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NCP1010, NCP1011,
NCP1012, NCP1013,
NCP1014
Self-Supplied Monolithic
Switcher for Low Standby-
Power Offline SMPS
The NCP101X series integrates a fixed−frequency current−mode
controller and a 700 V MOSFET. Housed in a PDIP−7 or SOT−223
package, the NCP101X offers everything needed to build a rugged and
low−cost power supply, including soft−start, frequency jittering,
short−circuit protection, skip−cycle, a maximum peak current setpoint
and a Dynamic Self−Supply (no need for an auxiliary winding).
Unlike other monolithic solutions, the NCP101X is quiet by nature:
during nominal load operation, the part switches at one of the available
frequencies (65 − 100 − 130 kHz). When the current setpoint falls
below a given value, e.g. the output power demand diminishes, the IC
automatically enters the so−called skip−cycle mode and provides
excellent efficiency at light loads. Because this occurs at typically 1/4
of the maximum peak value, no acoustic noise takes place. As a result,
standby power is reduced to the minimum without acoustic noise
generation.
Short−circuit detection takes place when the feedback signal fades
away, e.g. in true short−circuit conditions or in broken Optocoupler
cases. External disabling is easily done either simply by pulling the
feedback pin down or latching it to ground through an inexpensive
SCR for complete latched−off. Finally soft−start and frequency
jittering further ease the designer task to quickly develop low−cost and
robust offline power supplies.
For improved standby performance, the connection of an auxiliary
winding stops the DSS operation and helps to consume less than
100 mW at high line. In this mode, a built−in latched overvoltage
protection prevents from lethal voltage runaways in case the
Optocoupler would brake. These devices are available in economical
8−pin dual−in−line and 4−pin SOT−223 packages.
http://onsemi.com
MARKING
DIAGRAMS
4
4 SOT−223
CASE 318E
1 ST SUFFIX
AYW
101xy G
G
1
8
1
PDIP−7
CASE 626A
AP SUFFIX
P101xAPyy
AWL
YYWWG
1
x = Current Limit (0, 1, 2, 3, 4)
y = Oscillator Frequency
A (65 kHz), B (100 kHz), C (130 kHz)
yy = 06 (65 kHz), 10 (100 kHz), 13 (130 kHz)
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
Features
Built−in 700 V MOSFET with Typical RDSon of 11 W
and 22 W
Large Creepage Distance Between High−Voltage Pins
Current−Mode Fixed Frequency Operation:
65 kHz – 100 kHz − 130 kHz
Skip−Cycle Operation at Low Peak Currents Only:
No Acoustic Noise!
Dynamic Self−Supply, No Need for an Auxiliary
Winding
Internal 1.0 ms Soft−Start
Latched Overvoltage Protection with Auxiliary
Winding Operation
Frequency Jittering for Better EMI Signature
Auto−Recovery Internal Output Short−Circuit
Protection
Below 100 mW Standby Power if Auxiliary Winding
is Used
Internal Temperature Shutdown
Direct Optocoupler Connection
SPICE Models Available for TRANsient Analysis
These are Pb−Free and Halide−Free Devices
Typical Applications
Low Power AC/DC Adapters for Chargers
Auxiliary Power Supplies (USB, Appliances,TVs, etc.)
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 23
1
Publication Order Number:
NCP1010/D

1 page




NCP1010 pdf
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 8.0 V unless otherwise noted.)
Rating
Pin Symbol Min Typ Max Unit
SUPPLY SECTION AND VCC MANAGEMENT
VCC Increasing Level at which the Current Source Turns−off
VCC Decreasing Level at which the Current Source Turns−on
Hysteresis between VCCOFF and VCCON
VCC Decreasing Level at which the Latch−off Phase Ends
VCC Decreasing Level at which the Internal Latch is Released
Internal IC Consumption, MOSFET Switching at 65 kHz (Note 2)
Internal IC Consumption, MOSFET Switching at 100 kHz (Note 2)
Internal IC Consumption, MOSFET Switching at 130 kHz (Note 2)
Internal IC Consumption, Latch−off Phase, VCC = 6.0 V
Active Zener Voltage Positive Offset to VCCOFF
Latch−off Current
NCP1012/13/14
NCP1010/11
0°C < TJ < 125°C
−40°C < TJ < 125°C
0°C < TJ < 125°C
−40°C < TJ < 125°C
POWER SWITCH CIRCUIT
Power Switch Circuit On−state Resistance
NCP1012/13/14 (Id = 50 mA)
TJ = 25°C
TJ = 125°C
NCP1010/11 (Id = 50 mA)
TJ = 25°C
TJ = 125°C
Power Switch Circuit and Startup Breakdown Voltage
(ID(off) = 120 mA, TJ = 25°C)
Power Switch and Startup Breakdown Voltage Off−state Leakage Current
TJ = −40°C (Vds = 650 V)
TJ = 25°C (Vds = 700 V)
TJ = 125°C (Vds = 700 V)
Switching Characteristics (RL = 50 W, Vds Set for Idrain = 0.7 x Ilim)
Turn−on Time (90%−10%)
Turn−off Time (10%−90%)
1 VCCOFF
1 VCCON
1−
7.9
6.9
1 VCClatch
1 VCCreset
1 ICC1
4.4
1 ICC1
1 ICC1
1 ICC2
1 Vclamp 140
1 ILatch
6.3
5.8
5.8
5.3
8.5
7.5
1.0
4.7
3.0
0.92
0.95
0.98
290
200
7.4
7.4
7.3
7.3
9.1 V
8.1 V
−V
5.1 V
−V
1.1 mA
1.15 mA
1.2 mA
mA
300 mV
mA
9.2
9.2
9.0
9.0
5 RDSon
5 BVdss 700
11
19
22
38
W
16
24
35
50
−V
IDS(OFF)
5
5
5
5 ton
5 toff
mA
70 120
50 −
30 −
ns
20 −
10 −
INTERNAL STARTUP CURRENT SOURCE
High−voltage Current Source, VCC = 8.0 V
NCP1012/13/14
0°C < TJ < 125°C
−40°C < TJ < 125°C
NCP1010/11
0°C < TJ < 125°C
−40°C < TJ < 125°C
High−voltage Current Source, VCC = 0
CURRENT COMPARATOR TJ = 25°C (Note 2)
Maximum Internal Current Setpoint, NCP1010 (Note 3)
Maximum Internal Current Setpoint, NCP1011 (Note 3)
Maximum Internal Current Setpoint, NCP1012 (Note 3)
Maximum Internal Current Setpoint, NCP1013 (Note 3)
Maximum Internal Current Setpoint, NCP1014 (Note 3)
Default Internal Current Setpoint for Skip−Cycle Operation, Percentage of
Max Ip
1 IC1
1 IC2
mA
5.0 8.0 10
5.0 8.0 11
5.0 8.0 10.3
5.0 8.0 11.5
− 10 − mA
5 Ipeak (22) 90
100 110 mA
5 Ipeak (22) 225 250 275 mA
5 Ipeak (11) 225 250 275 mA
5 Ipeak (11) 315 350 385 mA
5 Ipeak (11) 405 450 495 mA
− ILskip − 25 − %
Propagation Delay from Current Detection to Drain OFF State
Leading Edge Blanking Duration
2. See characterization curves for temperature evolution.
3. Adjust di/dt to reach Ipeak in 3.2 msec.
− TDEL
− TLEB
− 125 − ns
− 250 − ns
http://onsemi.com
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NCP1010 arduino
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Plugging Equations 7 and 8 into Equation 6 leads to
t Vds(t) u+ Vin and thus, PDSS + Vin ICC1 (eq. 9) .
The worse case occurs at high line, when Vin equals
370 Vdc. With ICC1 = 1.1 mA (65 kHz version), we can
expect a DSS dissipation around 407 mW. If you select a
higher switching frequency version, the ICC1 increases and
it is likely that the DSS consumption exceeds that number.
In that case, we recommend to add an auxiliary winding in
order to offer more dissipation room to the power MOSFET.
Please read application note AND8125/D, “Evaluating
the Power Capability of the NCP101X Members” to help in
selecting the right part/configuration for your application.
Lowering the Standby Power with an Auxiliary Winding
The DSS operation can bother the designer when its
dissipation is too high and extremely low standby power is
a must. In both cases, one can connect an auxiliary winding
to disable the self−supply. The current source then ensures
the startup sequence only and stays in the off state as long as
VCC does not drop below VCCON or 7.5 V. Figure 18 shows
that the insertion of a resistor (Rlimit) between the auxiliary
DC level and the VCC pin is mandatory to not damage the
internal 8.7 V active Zener diode during an overshoot for
instance (absolute maximum current is 15 mA) and to
implement the fail−safe optocoupler protection as offered by
the active clamp. Please note that there cannot be bad
interaction between the clamping voltage of the internal
Zener and VCCOFF since this clamping voltage is actually
built on top of VCCOFF with a fixed amount of offset
(200 mV typical).
Self−supplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a SMPS
operated at nominal load can deliver an auxiliary voltage of
an arbitrary 16 V (Vnom), this voltage can drop to below
10 V (Vstby) when entering standby. This is because the
recurrence of the switching pulses expands so much that the
low frequency refueling rate of the VCC capacitor is not
enough to keep a constant auxiliary voltage. Figure 19
portrays a typical scope shot of a SMPS entering deep
standby (output unloaded). So care must be taken when
calculating Rlimit 1) to not trigger the VCC over current
latch [by injecting 6.3 mA (min. value) into the active
clamp] in normal operation but 2) not to drop too much
voltage over Rlimit when entering standby. Otherwise the
DSS could reactivate and the standby performance would
degrade. We are thus able to bound Rlimit between two
equations:
Vnom
* Vclamp
Itrip
v
Rlimit
v
Vstby
* VCCON
ICC1
(eq. 10)
Where:
Vnom is the auxiliary voltage at nominal load.
Vstdby is the auxiliary voltage when standby is entered.
Itrip is the current corresponding to the nominal operation.
It must be selected to avoid false tripping in overshoot
conditions.
ICC1 is the controller consumption. This number slightly
decreases compared to ICC1 from the spec since the part in
standby almost does not switch.
VCCON is the level above which Vaux must be maintained
to keep the DSS in the OFF mode. It is good to shoot around
8.0 V in order to offer an adequate design margin, e.g. to not
reactivate the startup source (which is not a problem in itself
if low standby power does not matter).
Since Rlimit shall not bother the controller in standby, e.g.
keep Vaux to around 8.0 V (as selected above), we purposely
select a Vnom well above this value. As explained before,
experience shows that a 40% decrease can be seen on
auxiliary windings from nominal operation down to standby
mode. Let’s select a nominal auxiliary winding of 20 V to
offer sufficient margin regarding 8.0 V when in standby
(Rlimit also drops voltage in standby). Plugging the
values in Equation 10 gives the limits within which Rlimit
shall be selected:
20 * 8.7
6.3 m
v
Rlimit
v
12 * 8
1.1 m
,
that
is
to
say:
1.8 k t Rlimit t 3.6 k
(eq. 11)
If we design a power supply delivering 12 V, then the ratio
between auxiliary and power must be: 12/20 = 0.6. The OVP
latch will activate when the clamp current exceeds 6.3 mA.
This will occur when Vaux increases to: 8.7 V + 1.8 k x
(6.4m + 1.1m) = 22.2 V for the first boundary or 8.7 V +
3.6 k x (6.4m +1.1m) = 35.7 V for second boundary. On the
power output, it will respectively give 22.2 x 0.6 = 13.3 V
and 35.7 x 0.6 = 21.4 V. As one can see, tweaking the Rlimit
value will allow the selection of a given overvoltage output
level. Theoretically predicting the auxiliary drop from
nominal to standby is an almost impossible exercise since
many parameters are involved, including the converter time
constants. Fine tuning of Rlimit thus requires a few
iterations and experiments on a breadboard to check Vaux
variations but also output voltage excursion in fault. Once
properly adjusted, the fail−safe protection will preclude any
lethal voltage runaways in case a problem would occur in the
feedback loop.
When an OVP occurs, all switching pulses are
permanently disabled, the output voltage thus drops to zero.
The VCC cycles up and down between 8.5–4.7 V and stays
in this state until the user unplugs the power supply and
forces VCC to drop below 3.0 V (VCCreset). Below this
value, the internal OVP latch is reset and when the high
voltage is reapplied, a new startup sequence can take place
in an attempt to restart the converter.
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