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PDF N74F195AN Data sheet ( Hoja de datos )
| Número de pieza | N74F195AN | |
| Descripción | 4-bit parallel-access shift register | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
74F195A
4-bit parallel-access shift register
Product specification
IC15 Data Handbook
1996 Mar 12
Philips
Semiconductors
1 page  
Philips Semiconductors
4-bit parallel-access shift register
Product specification
74F195A
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONSNO TAG
LIMITS
MIN
TYP
NO TAG
MAX
UNIT
VOH High-level output voltage
VCC = MIN, VIL = MAX ±10%VCC
2.5
VIH = MIN, IOH = MAX
±5%VCC
2.7 3.4
V
V
VOL Low-level output voltage
VCC = MIN, VIL = MAX
VIH = MIN, IOL = MAX
±10%VCC
±5%VCC
0.35 0.50
0.35 0.50
V
VIK Input clamp voltage
VCC = MIN, II = IIK
–0.73 –1.2
V
II Input current at maximum input voltage VCC = MAX, VI = 7.0V 74F195A
100 µA
IIH High-level input current
VCC = MAX, VI = 2.7V all others
20 µA
IIL Low-level input current
IOS Short-circuit output current3
VCC = MAX, VI = 0.5V 74F195A
VCC = MAX
–60
–600
–150
mA
mA
ICC Supply current (total)
VCC = MAX
74F195A
40 58
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
fMAX
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
Maximum clock
frequency
Propagation delay
CP to Qn
Propagation delay
CP to Q3
Propagation delay
MR to Qn
Propagation delay
MR to Q3
Load mode
Shift mode
TEST
CONDITION
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform 2
Waveform 2
LIMITS
VCC = +5V
Tamb = +25°C
CL = 50pF, RL = 500Ω
MIN TYP MAX
VCC = +5V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500Ω
MIN MAX
165 180
150
180 190
170
3.0 5.0 9.5
2.5 4.0 7.0
2.5
2.0
10.0
7.5
2.0 5.5 9.5
2.0 4.0 6.5
2.5
2.0
9.5
7.0
2.0 4.0 7.0
2.0
7.0
2.5 4.5 8.0
2.0
10.0
UNIT
MHz
ns
ns
ns
ns
1996 Mar 12
5
5 Page | ||
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