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PDF 93C66 Data sheet ( Hoja de datos )
| Número de pieza | 93C66 | |
| Descripción | 4096-Bit Serial CMOS EEPROM (MICROWIRE Synchronous Bus) | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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July 2000
FM93C66
4096-Bit Serial CMOS EEPROM
(MICROWIRE™ Synchronous Bus)
General Description
FM93C66 is a 4096-bit CMOS non-volatile EEPROM organized
as 256 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat-
ible to many of standard Microcontrollers and Microprocessors.
There are 7 instructions implemented on the FM93C66 for various
Read, Write, Erase, and Write Enable/Disable operations. This
device is fabricated using Fairchild Semiconductor floating-gate
CMOS process for high reliability, high endurance and low power
consumption.
“LZ” and “L” versions of FM93C66 offer very low standby current
making them suitable for low power applications. This device is
offered in both SO and TSSOP packages for small space consid-
erations.
Features
I Wide VCC 2.7V - 5.5V
I Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I No Erase instruction required before Write instruction
I Self timed write cycle
I Device status during programming cycles
I 40 year data retention
I Endurance: 1,000,000 data changes
I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
CS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
DECODER
EEPROM ARRAY
16
READ/WRITE AMPS
16
DATA IN/OUT REGISTER
16 BITS
DO DATA OUT BUFFER
VCC
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
VSS
© 2000 Fairchild Semiconductor International
FM93C66 Rev. C.1
1
www.fairchildsemi.com
1 page  
Pin Description
Chip Select (CS)
This is an active high input pin to FM93C66 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input informa-
tion (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
Serial Input (DI)
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input informa-
tion (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
Serial Output (DO)
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Microwire Interface
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array, a set of 7 instructions are implemented on FM93C66.
The format of each instruction is listed under Table 1.
Instruction
Each of the 7 instructions is explained under individual instruction
descriptions.
Start bit
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be “1” for a valid cycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
Opcode
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with 2 MSB of address field) select a
particular instruction to be executed.
Address Field
This is an 8-bit field and should immediately follow the Opcode bits.
In FM93C66, all 8 bits are used for address decoding during READ,
WRITE and ERASE instructions. During all other instructions, the
MSB 2 bits are used to decode instruction (along with Opcode bits).
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
Table 1. Instruction set
Instruction
READ
WEN
WRITE
WRALL
WDS
ERASE
ERAL
Start Bit Opcode Field
Address Field
Data Field
1 10 A7 A6 A5 A4 A3 A2 A1 A0
1 00 1 1 X X X X X X
1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0
1 00 0 1 X X X X X X D15-D0
1 00 0 0 X X X X X X
1 11 A7 A6 A5 A4 A3 A2 A1 A0
1 00 1 0 X X X X X X
FM93C66 Rev. C.1
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
87 65
0.228 - 0.244
(5.791 - 6.198)
0.010 - 0.020 x 45¡
(0.254 - 0.508)
0.150 - 0.157
(3.810 - 3.988)
8¡ Max, Typ.
All leads
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.004
(0.102)
All lead tips
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
12 34
Lead #1
IDENT
0.053 - 0.069
(1.346 - 1.753)
0.014
(0.356)
0.050
(1.270)
Typ
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
Package Number M08A
FM93C66 Rev. C.1
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet 93C66.PDF ] | |
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