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PDF 93C46 Data sheet ( Hoja de datos )
| Número de pieza | 93C46 | |
| Descripción | 1K Microwire Serial EEPROM | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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93AA46, 93LC46, 93C46
93AA46A/B, 93LC46A/B, 93C46A/B
1K Microwire® Serial EEPROM
Device Selection Table
Part
Number
93AA46
93LC46
93C46
93AA46A
93AA46B
93LC46A
93LC46B
93C46A
93C46B
VCC
Range
1.8-5.5
2.5-5.5
4.5-5.5
1.8-5.5
1.8-5-5
2.5-5.5
2.5-5.5
4.5-5.5
4.5-5.5
Org Pin Word Size
Temp
Ranges
Yes 8 or 16-bit
I
Yes 8 or 16-bit I, E
Yes 8 or 16-bit I, E
No 8-bit
I
No 16-bit
I
No 8-bit
I, E
No 16-bit
I, E
No 8-bit
I, E
No 16-bit
I, E
Features
• Low power CMOS technology
• ORG pin for selectable memory configuration
• No org pin for dedicated word sizes
- 128 x 8-bit organization ‘A’ version devices
- 64 x 16-bit organization ‘B’ version devices
• Self-timed ERASE and WRITE cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 1,000,000 E/W cycles
• Data retention > 200 years
• 8-pin MSOP and 6-pin SOT
• Temperature ranges supported:
- Industrial (I):
-40°C to +85°C
- Automotive (E)
-40°C to +125°C
Package Types
MSOP
CS
CLK
DI
DO
1
2
3
4
8 VCC
7 NU
6 ORG*
5 VSS
* Org pin is not available on A/B devices
Description
The Microchip Technology Inc. 93AA46, 93LC46,
93C46, 93AA46A/B, 93LC46A/B & 93C46A/B are 1K
low voltage serial Electrically Erasable PROMs
(EEPROM). Generic memory devices such as the
93AA46, 93LC46 or 93C46 are dependent upon exter-
nal logic levels driving the ORG pin to set word size.
For dedicated 8-bit communication, the 93AA46A,
93LC46A or 93C46A devices are selected, while the
93AA46B, 93LC46B and 93C46B devices are selected
for 16 bits. Advanced CMOS technology makes these
devices ideal for low power, non-volatile memory
applications. This 93XX Series is available in standard
8-lead MSOP and 6-lead SOT-23 packages.
Block Diagram
VCC VSS
MEMORY
ARRAY
ADDRESS
DECODER
DI
ORG*
CS
DATA REGISTER
MODE
DECODE
LOGIC
ADDRESS
COUNTER
OUTPUT
BUFFER
DO
CLK
CLOCK
REGISTER
* Org input is not available on A/B devices
SOT-23**
DO 1
VSS 2
DI 3
6 VCC
5 CS
4 CLK
** SOT-23 device only offered in A/B versions
2002 Microchip Technology Inc.
DS21749A-page 1
1 page  
2.0 FUNCTIONAL DESCRIPTION
When the ORG* pin is connected to VCC, the (x16)
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instructions,
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is nor-
mally held in a high-Z state except when reading data
from the device, or when checking the READY/BUSY
status during a programming operation. The ready/
busy status can be verified during an Erase/Write oper-
ation by polling the DO pin; DO low indicates that pro-
gramming is still in progress, while DO high indicates
the device is ready. The DO will enter the high-Z state
on the falling edge of the CS.
2.1 START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the Standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new START condition is
detected.
93XX46, 93XX46A/B
2.2 Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic
HIGH level. Under such a condition the voltage level
seen at Data Out is undefined and will depend upon the
relative impedances of Data Out and the signal source
driving A0. The higher the current sourcing capability of
A0, the higher the voltage at the Data Out pin.
2.3 Data Protection
During power-up, all programming modes of operation
are inhibited until VCC exceeds a typical voltage level of
1.5V for 'AA' and 'LC' devices or 3.8V for 'C' devices.
During power-down, the source data protection cir-
cuitry acts to inhibit all programming modes when VCC
falls below 1.4V for 'AA' and 'LC' devices or 3.5V for 'C'
devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
*Org pin is not available on A/B devices
2002 Microchip Technology Inc.
DS21749A-page 5
5 Page 
93XX46, 93XX46A/B
3.0 PIN DESCRIPTIONS
FIGURE 3-1: PIN DESCRIPTIONS
Name
MSOP
6-LEAD
SOT-23
Function
CS 1
5
Chip Select
CLK 2
4
Serial Clock
DI 3
3
Data In
DO 4
1
Data Out
Vss 5
2
Ground
ORG/NC
6
N/A Organization / No Connect
(No internal connection for 93XX46A/B)
NC 7 N/A No Connect (No Internal Connection)
Vcc 8
6
Power Supply
3.1 CHIP SELECT (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However,
a programming cycle which is already in progress will
be completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a RESET status.
Input filter spike suppression was added to reduce
susceptibility to noise.
3.2 SERIAL CLOCK (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a START condition the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become don't care inputs waiting for a new START
condition to be detected.
Input filter spike suppression was added to reduce
susceptibility to noise.
3.3 DATA IN (DI)
Data In (DI) is used to clock in a START bit, opcode,
address and data synchronously with the CLK input.
Input filter spike suppression was added to reduce
susceptibility to noise.
3.4 DATA OUT (DO)
Data Out (DO) is used in the READ mode to output
data synchronously with the CLK input (TPD after the
positive edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
3.5 ORGANIZATION (ORG)*
When the ORG pin is connected to VCC or Logic HI, the
(x16) memory organization is selected. When the ORG
pin is tied to VSS or Logic LO, the (x8) memory organi-
zation is selected. For proper operation, ORG must be
tied to a valid logic level.
On the dedicated 'A' and 'B' devices the user selectable
ORG function is not present. (No internal connection.)
2002 Microchip Technology Inc.
DS21749A-page 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet 93C46.PDF ] | |
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