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PDF NTD85N02RT4G Data sheet ( Hoja de datos )
| Número de pieza | NTD85N02RT4G | |
| Descripción | Power MOSFET 85 Amps / 24 Volts N-Channel DPAK | |
| Fabricantes | ON | |
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NTD85N02R
Power MOSFET
85 Amps, 24 Volts
N−Channel DPAK
Features
• Pb−Free Packages are Available
• Planar HD3e Process for Fast Switching Performance
• Low RDS(on) to Minimize Conduction Loss
• Low Ciss to Minimize Driver Loss
• Low Gate Charge
MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current
Continuous @ TC = 25°C, Limited by Package
Continuous @ TA = 25°C, Limited by Wires
Single Pulse (tp ≤ 10 ms)
Thermal Resistance, Junction−to−Ambient
(Note 1)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
Thermal Resistance, Junction−to−Ambient
(Note 2)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
Operating and Storage Temperature Range
VDSS
VGS
RqJC
PD
24
±20
1.6
78.1
Vdc
Vdc
°C/W
W
ID
ID
IDM
RqJA
85 A
32 A
96 A
52 °C/W
PD
ID
RqJA
2.4 W
16 A
100 °C/W
PD
ID
TJ, Tstg
1.25
12
−55 to
150
W
A
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 10 Vdc, IL = 13 Apk,
L = 1 mH, RG = 25 W)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
EAS 85 mJ
TL 260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR4 board using 1 inch pad size,
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in2).
http://onsemi.com
VDSS
24 V
RDS(ON) TYP
4.8 mW
ID MAX
85 A
N−Channel
D
G
S
4
4
12
3
DPAK
CASE 369C
STYLE2
12
3
DPAK−3
CASE 369D
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
1 YWW
2 85
3 N02
1 Gate
4 2 Drain
3 Source
4 Drain
Y = Year
WW = Work Week
85N02R = Specific Device Code
123
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2004
September, 2004 − Rev. 6
1
Publication Order Number:
NTD85N02R/D
1 page  
NTD85N02R
6
4
Q1
QT
Q2
1000
VGS
100
2
ID = 10 A
TJ = 25°C
0
0 4 8 12 16 20
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
10
1
1
tr
td(off)
tf
td(on)
VDS = 10 V
ID = 40 A
VGS = 10 V
10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
80
VGS = 0 V
70
60
50
40
30
20
10
TJ = 25°C
0
0 0.2 0.4 0.6 0.8 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
http://onsemi.com
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