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PDF 8XC552 Data sheet ( Hoja de datos )

Número de pieza 8XC552
Descripción 80C51 FAMILY DERIVATIVES
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! 8XC552 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
80C51 FAMILY DERIVATIVES
8XC552/562 overview
1996 Aug 06
Philips
Semiconductors

1 page




8XC552 pdf
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
Table 1. 8XC552 Special Function Registers (Continued)
SYMBOL DESCRIPTION
PWMP#
PWM1#
PWM0#
PWM prescaler
PWM register 1
PWM register 0
DIRECT
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
ADDRESS MSB
LSB
FEH
FDH
FCH
RESET
VALUE
00H
00H
00H
RTE#
Reset/toggle enable
EFH
TP47 TP46 RP45 RP44 RP43 RP42 RP41 RP40 00H
SP Stack pointer
81H
07H
S0BUF
Serial 0 data buffer
99H
xxxxxxxxB
9F 9E
9D
9C
9B
9A
99
98
S0CON* Serial 0 control
98H SM0 SM1 SM2 REN TB8 RB8 TI
RI 00H
S1ADR#
SIDAT#
Serial 1 address
Serial 1 data
DBH
DAH
 SLAVE ADDRESS 
GC 00H
00H
S1STA# Serial 1 status
D9H
SC4 SC3 SC2 SC1 SC0
0
0
0 F8H
DF DE
DD
DC
DB
DA
D9
D8
SICON#* Serial 1 control
D8H
CR2 ENS1 STA
ST0
SI
AA
CR1
CR0 00H
STE#
Set enable
EEH
TG47 TG46 SP45 SP44 SP43 SP42 SP41 SP40 C0H
TH1
TH0
TL1
TL0
TMH2#
TML2#
Timer high 1
Timer high 0
Timer low 1
Timer low 0
Timer high 2
Timer low 2
8DH
8CH
8BH
8AH
EDH
ECH
TMOD
Timer mode
89H GATE
8F
TCON*
Timer control
88H TF1
TM2CON# Timer 2 control
EAH
T2IS1
CF
TM2IR#* Timer 2 int flag reg
C8H
T20V
T3# Timer 3
FFH
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
C/T
8E
TR1
T2IS0
CE
CMI2
M1
8D
TF0
T2ER
CD
CMI1
M0
8C
TR0
T2B0
CC
CMI0
GATE
8B
IE1
T2P1
CB
CTI3
C/T
8A
IT1
T2P0
CA
CTI2
M1
89
IE0
T2MS1
C9
CTI1
00H
00H
00H
00H
00H
00H
M0 00H
88
IT0 00H
T2MS0 00H
C8
CTI0 00H
00H
IEN1 (E8H)
7
ET2
(MSB)
6
ECM2
5
ECM1
4
ECM0
3
ECT3
2
ECT2
1
ECT1
0
ECT0
(LSB)
BIT
IEN1.7
IEN1.6
IEN1.5
IEN1.4
IEN1.3
IEN1.2
IEN1.1
IEN1.0
SYMBOL
ET2
ECM2
ECM1
ECM0
ECT3
ECT2
ECT1
ECT0
FUNCTION
Enable Timer T2 overflow interrupt(s)
Enable T2 Comparator 2 interrupt
Enable T2 Comparator 1 interrupt
Enable T2 Comparator 0 interrupt
Enable T2 Capture register 3 interrupt
Enable T2 Capture register 2 interrupt
Enable T2 Capture register 1 interrupt
Enable T2 Capture register 0 interrupt
Figure 2. Timer T2 Interrupt Enable Register (IEN1)
SU00755
1996 Aug 06
5

5 Page





8XC552 arduino
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
The CPU interfaces to the I2C logic via the following four special
function registers: S1CON (SIO1 control register), S1STA (SIO1
status register), S1DAT (SIO1 data register), and S1ADR (SIO1
slave address register). The SIO1 logic interfaces to the external I2C
bus via two port 1 pins: P1.6/SCL (serial clock line) and P1.7/SDA
(serial data line).
A typical I2C bus configuration is shown in Figure 10, and Figure 11
shows how a data transfer is accomplished on the bus. Depending
on the state of the direction bit (R/W), two types of data transfers are
possible on the I2C bus:
1. Data transfer from a master transmitter to a slave receiver. The
first byte transmitted by the master is the slave address. Next
follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2. Data transfer from a slave transmitter to a master receiver. The
first byte (the slave address) is transmitted by the master. The
slave then returns an acknowledge bit. Next follows the data
bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last
byte. At the end of the last received byte, a “not acknowledge” is
returned.
The master device generates all of the serial clock pulses and the
START and STOP conditions. A transfer is ended with a STOP
condition or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial transfer, the
I2C bus will not be released.
Modes of Operation: The on-chip SIO1 logic may operate in the
following four modes:
1. Master Transmitter Mode:
Serial data output through P1.7/SDA while P1.6/SCL outputs the
serial clock. The first byte transmitted contains the slave address
of the receiving device (7 bits) and the data direction bit. In this
case the data direction bit (R/W) will be logic 0, and we say that
a “W” is transmitted. Thus the first byte transmitted is SLA+W.
Serial data is transmitted 8 bits at a time. After each byte is
transmitted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the end of a
serial transfer.
2. Master Receiver Mode:
The first byte transmitted contains the slave address of the
transmitting device (7 bits) and the data direction bit. In this case
the data direction bit (R/W) will be logic 1, and we say that an “R”
is transmitted. Thus the first byte transmitted is SLA+R. Serial
data is received via P1.7/SDA while P1.6/SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each byte is
received, an acknowledge bit is transmitted. START and STOP
conditions are output to indicate the beginning and end of a
serial transfer.
3. Slave Receiver Mode:
Serial data and the serial clock are received through P1.7/SDA
and P1.6/SCL. After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave address and
direction bit.
4. Slave Transmitter Mode:
The first byte is received and handled as in the slave receiver
mode. However, in this mode, the direction bit will indicate that
the transfer direction is reversed. Serial data is transmitted via
P1.7/SDA while the serial clock is input through P1.6/SCL.
START and STOP conditions are recognized as the beginning
and end of a serial transfer.
In a given application, SIO1 may operate as a master and as a
slave. In the slave mode, the SIO1 hardware looks for its own slave
address and the general call address. If one of these addresses is
detected, an interrupt is requested. When the microcontroller wishes
to become the bus master, the hardware waits until the bus is free
before the master mode is entered so that a possible slave action is
not interrupted. If bus arbitration is lost in the master mode, SIO1
switches to the slave mode immediately and can detect its own
slave address in the same serial transfer.
SIO1 Implementation and Operation: Figure 12 shows how the
on-chip I2C bus interface is implemented, and the following text
describes the individual blocks.
INPUT FILTERS AND OUTPUT STAGES
The input filters have I2C compatible input levels. If the input voltage
is less than 1.5V, the input logic level is interpreted as 0; if the input
voltage is greater than 3.0V, the input logic level is interpreted as 1.
Input signals are synchronized with the internal clock (fOSC/4), and
spikes shorter than three oscillator periods are filtered out.
The output stages consist of open drain transistors that can sink
3mA at VOUT < 0.4V. These open drain outputs do not have
clamping diodes to VDD. Thus, if the device is connected to the I2C
bus and VDD is switched off, the I2C bus is not affected.
ADDRESS REGISTER, S1ADR
This 8-bit special function register may be loaded with the 7-bit slave
address (7 most significant bits) to which SIO1 will respond when
programmed as a slave transmitter or receiver. The LSB (GC) is
used to enable general call address (00H) recognition.
COMPARATOR
The comparator compares the received 7-bit slave address with its
own slave address (7 most significant bits in S1ADR). It also
compares the first received 8-bit byte with the general call address
(00H). If an equality is found, the appropriate status bits are set and
an interrupt is requested.
SHIFT REGISTER, S1DAT
This 8-bit special function register contains a byte of serial data to
be transmitted or a byte which has just been received. Data in
S1DAT is always shifted from right to left; the first bit to be
transmitted is the MSB (bit 7) and, after a byte has been received,
the first bit of received data is located at the MSB of S1DAT. While
data is being shifted out, data on the bus is simultaneously being
shifted in; S1DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master
transmitter to slave receiver is made with the correct data in S1DAT.
1996 Aug 06
11

11 Page







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