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PDF 89C2051 Data sheet ( Hoja de datos )
| Número de pieza | 89C2051 | |
| Descripción | 8-Bit Microcontroller with 2K Bytes Flash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Compatible with MCS-51™ Products
• 2K Bytes of Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• 2.7V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Two-Level Program Memory Lock
• 128 x 8-Bit Internal RAM
• 15 Programmable I/O Lines
• Two 16-Bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial UART Channel
• Direct LED Drive Outputs
• On-Chip Analog Comparator
• Low Power Idle and Power Down Modes
Description
The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with
2K Bytes of Flash programmable and erasable read only memory (PEROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatible with the industry standard MCS-51™ instruction set. By combining
a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a pow-
erful microcomputer which provides a highly flexible and cost effective solution to
many embedded control applications.
The AT89C2051 provides the following standard features: 2K Bytes of Flash, 128
bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt
architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator
and clock circuitry. In addition, the AT89C2051 is designed with static logic for opera-
tion down to zero frequency and supports two software selectable power saving
modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial
port and interrupt system to continue functioning. The Power Down Mode saves the
RAM contents but freezes the oscillator disabling all other chip functions until the next
hardware reset.
8-Bit
Microcontroller
with 2K Bytes
Flash
AT89C2051
Pin Configuration
PDIP/SOIC
/VPP
0368D-B–12/97
4-15
1 page  
AT89C2051
Restrictions on Certain Instructions
The AT89C2051 and is an economical and cost-effective
member of Atmel’s growing family of microcontrollers. It
contains 2K bytes of flash program memory. It is fully com-
patible with the MCS-51 architecture, and can be pro-
grammed using the MCS-51 instruction set. However,
there are a few considerations one must keep in mind when
utilizing certain instructions to program this device.
All the instructions related to jumping or branching should
be restricted such that the destination address falls within
the physical program memory space of the device, which is
2K for the AT89C2051. This should be the responsibility of
the software programmer. For example, LJMP 7E0H would
be a valid instruction for the AT89C2051 (with 2K of mem-
ory), whereas LJMP 900H would not.
1. Branching instructions:
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR
These unconditional branching instructions will execute
correctly as long as the programmer keeps in mind that the
destination branching address must fall within the physical
boundaries of the program memory size (locations 00H to
7FFH for the 89C2051). Violating the physical space limits
may cause unknown program behavior.
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With
these conditional branching instructions the same rule
above applies. Again, violating the memory boundaries
may cause erratic execution.
For applications involving interrupts the normal interrupt
service routine address locations of the 80C51 family archi-
tecture have been preserved.
2. MOVX-related instructions, Data Memory:
The AT89C2051 contains 128 bytes of internal data mem-
ory. Thus, in the AT89C2051 the stack depth is limited to
128 bytes, the amount of available RAM. External DATA
memory access is not supported in this device, nor is exter-
nal PROGRAM memory execution. Therefore, no MOVX
[...] instructions should be included in the program.
A typical 80C51 assembler will still assemble instructions,
even if they are written in violation of the restrictions men-
tioned above. It is the responsibility of the controller user to
know the physical features and limitations of the device
being used and adjust the instructions used correspond-
ingly.
Program Memory Lock Bits
On the chip are two lock bits which can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the table below:
Lock Bit Protection Modes(1)
Program Lock Bits
LB1 LB2 Protection Type
1 U U No program lock features.
2 P U Further programming of the Flash
is disabled.
3
Note:
P P Same as mode 2, also verify is
disabled.
1. The Lock Bits can only be erased with the Chip Erase
operation.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
P1.0 and P1.1 should be set to ’0’ if no external pullups are
used, or set to ’1’ if external pullups are used.
It should be noted that when idle is terminated by a hard-
ware reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external
memory.
Power Down Mode
In the power down mode the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before VCC is
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta-
bilize.
P1.0 and P1.1 should be set to ’0’ if no external pullups are
used, or set to ’1’ if external pullups are used.
4-19
5 Page 
AT89C2051
Serial Port Timing: Shift Register Mode Test Conditions
(VCC = 5.0V ± 20%; Load Capacitance = 80 pF)
Symbol
Parameter
12 MHz Osc
Variable Oscillator
Min Max
Min
Max
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
1.0 12tCLCL
700 10tCLCL-133
50 2tCLCL-117
00
700 10tCLCL-133
Units
µs
ns
ns
ns
ns
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms(1) Float Waveforms(1)
Note:
1. AC Inputs during testing are driven at VCC - 0.5V for
a logic 1 and 0.45V for a logic 0. Timing measure-
ments are made at VIH min. for a logic 1 and VIL
max. for a logic 0.
Note:
1. For timing purposes, a port pin is no longer float-
ing when a 100 mV change from load voltage
occurs. A port pin begins to float when 100 mV
change frothe loaded VOH/VOL level occurs.
4-25
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