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PDF 87C196LA Data sheet ( Hoja de datos )
| Número de pieza | 87C196LA | |
| Descripción | CHMOS 16-BIT MICROCONTROLLER | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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PRODUCT PREVIEW
87C196LA
CHMOS 16-BIT MICROCONTROLLER
Automotive
s 20 MHz operation†
s 24 Kbytes of on-chip OTPROM
s 768 bytes of on-chip register RAM
s Register-to-register architecture
s Peripheral transaction server (PTS)
with high-speed, microcoded interrupt
service routines
s Six-channel/10-bit A/D with sample and
hold
s High-speed event processor array
— Six capture/compare channels
— Two compare-only channels
— Two 16-bit software timers
† 16 MHz standard; 20 MHz is speed premium
s Full-duplex serial I/O port with
dedicated baud-rate generator
s Enhanced full-duplex, synchronous
serial I/O port (SSIO)
s Programmable 8- or 16-bit external bus
s Optional clock doubler with
programmable clock output signal
s SFR register that indicates the source
of the last reset
s Design enhancements for EMI
reduction
s Oscillator failure detection circuitry
s Watchdog timer (WDT)
s –40° C to +125° C ambient temperature
s 52-pin PLCC package
NOTE
This datasheet contains information on products in the design phase of development.
The specifications are subject to change without notice. Verify with your local Intel sales
office that you have the latest datasheet before finalizing a design.
The 87C196LA is a high-performance 16-bit microcontroller. The 87C196LA is composed of a high-speed
core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a
dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave
transceivers; a six-channel A/D converter with sample and hold; a flexible timer/counter structure with
prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture
and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophis-
ticated, prioritized interrupt structure with programmable peripheral transaction server (PTS). The clock
doubler circuitry and oscillator output signal enable a 4 MHz resonator to achieve the same internal clock
speed as a more costly 8 MHz resonator in previous applications. This same circuitry can drive other devices
where a separate resonator was required in the past. Another cost-savings feature is the fact that the I/O
ports are driven low at reset, avoiding the need for pull-up resistors.
COPYRIGHT © INTEL CORPORATION, 1996
October 1996
Order Number: 272806-001
1 page  
2.0 PINOUT
AUTOMOTIVE — 87C196LA
AD14 / P4.6 / PBUS.14
AD13 / P4.5 / PBUS.13
AD12 / P4.4 / PBUS.12
AD11 / P4.3 / PBUS.11
AD10 / P4.2 / PBUS.10
AD9 / P4.1 / PBUS.9
AD8 / P4.0 / PBUS.8
AD7 / P3.7 / PBUS.7
AD6 / P3.6 / PBUS.6
AD5 / P3.5 / PBUS.5
AD4 / P3.4 / PBUS.4
AD3 / P3.3 / PBUS.3
AD2 / P3.2 / PBUS.2
8 46
9 45
10 44
11
12
AN87C196LA
43
42
13 41
14 40
15 View of component as 39
16
17
mounted on PC board
38
37
18 36
19 35
20 34
P6.1 / EPA9 / COMP1
P6.0 / EPA8 / COMP0
P1.0 / EPA0 / T2CLK
P1.1 / EPA1
P1.2 / EPA2 / T2DIR
P1.3 / EPA3
VREF
ANGND
P0.7 / ACH7 / PMODE.3
P0.6 / ACH6 / PMODE.2
P0.5 / ACH5 / PMODE.1
P0.4 / ACH4 / PMODE.0
P0.3 / ACH3
Figure 3. 87C196LA 52-pin Package
A3419-01
PRODUCT PREVIEW
5
5 Page 
AUTOMOTIVE — 87C196LA
Name
P5.3:2
P5.0
P6.7:4
P6.1:0
PACT#
PALE#
PBUS.15:0
PLLEN
PMODE.3:0
Type
I/O
O
O
I
I/O
I
I
Table 4. Signal Descriptions (Continued)
Description
Port 5
This is a memory-mapped, bidirectional port.
Port 5 shares package pins with the following signals: P5.0/ADV#/ALE,
P5.2/WR#/WRL#/PLLEN, and P5.3/RD#. P5.1 and P5.7:4 are not
implemented.
Port 6
This is a standardbidirectional port.
Port 6 shares package pins with the following signals: P6.0/EPA8/COMP0,
P6.1/EPA9/COMP1, P6.4/SC0, P6.5/SD0, P6.6/SC1, and P6.7/SD1.
Programming Active
During auto programming or slave dump, a low signal indicates that
programming or dumping is in progress, while a high signal indicates that the
operation is complete.
PACT# shares a package pin with P2.7 and OSCOUT.
Programming ALE
During slave programming, a falling edge causes the device to read a
command and address from the programming bus.
PALE# is multiplexed with P2.1 and RXD.
Address/Command/Data Bus
During slave programming, ports 3 and 4 serve as a bidirectional port with
open-drain outputs to pass commands, addresses, and data to or from the
device. Slave programming requires external pull-up resistors.
During auto programming and ROM-dump, ports 3 and 4 serve as a regular
system bus to access external memory. P4.6 and P4.7 are left unconnected;
P1.1 and P1.2 serve as the upper address lines.
Slave programming:
PBUS.7:0 share package pins with AD7:0 and P3.7:0.
PBUS.15:8 share package pins with AD15:8 and P4.7:0.
Auto programming:
PBUS.15:8 share package pins with AD15:8 and P4.7:0; PBUS.7:0 share
package pins with AD7:0 and P3.7:0.
Phase-locked Loop Enable
This active-high input pin enables the on-chip clock multiplier.
Programming Mode Select
These pins determine the programming mode. PMODE:0 are sampled after a
device reset and must be static while the microcontroller is operating.
PMODE:0 share package pins with P0.7:4 and ACH7:4.
PRODUCT PREVIEW
11
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet 87C196LA.PDF ] | |
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