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PDF 87C196KR Data sheet ( Hoja de datos )

Número de pieza 87C196KR
Descripción ADVANCED 16-BIT CHMOS MICROCONTROLLER
Fabricantes Intel Corporation 
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87C196KR KQ 87C196JV JT 87C196JR JQ
ADVANCED 16-BIT CHMOS MICROCONTROLLER
Automotive
Y b40 C to a125 C Ambient
Y High Performance CHMOS 16-Bit CPU
Y Up to 48 Kbytes of On-Chip EPROM
Y Up to 1 5 Kbytes of On-Chip Register
RAM
Y Up to 512 Bytes of Additional RAM
(Code RAM)
Y Register-Register Architecture
Y Up to 8 Channel 10-Bit A D with
Sample Hold
Y Up to 37 Prioritized Interrupt Sources
Y Up to Seven 8-Bit (56) I O Ports
Y Full Duplex Serial I O Port
Y Dedicated Baud Rate Generator
Y Interprocessor Communication Slave
Port
Y High Speed Peripheral Transaction
Server (PTS)
Y Two 16-Bit Software Timers
Y 10 High Speed Capture Compare (EPA)
Y Full Duplex Synchronous Serial I O
Port (SSIO)
Y Two Flexible 16-Bit Timer Counters
Y Quadrature Counting Inputs
Y Flexible 8- 16-Bit External Bus
Y Programmable Bus (HLD HLDA)
Y 1 75 ms 16 x 16 Multiply
Y 3 ms 32 16 Divide
Y 68-Pin and 52-Pin PLCC Packages
Device Pins Package EPROM Reg RAM Code RAM I O EPA SIO SSIO A D
87C196KR 68-pin PLCC
16K
488
256 56 10 Y Y 8
87C196KQ 68-pin PLCC
12K
360
128 56 10 Y Y 8
87C196JV 52-pin PLCC 48K 1 5K
512
41 6
Y
Y
6
87C196JT 52-pin PLCC 32K 1 0K
512
41 6
Y
Y
6
87C196JR 52-pin PLCC
16K
488
256
41 6
Y
Y
6
87C196JQ 52-pin PLCC
12K
360
128
41 6
Y
Y
6
The 87C196KR KQ JV JT JR JQ devices represent the fourth generation of MCS 96 Microcontroller prod-
ucts implemented on Intel’s advanced 1 micron process technology These products are based on the
80C196KB device with improvements for automotive applications The instruction set is a true super set of
80C196KB The 87C196JR is a 52-pin version of the 87C196KR device while the 87C196KQ JQ are memory
scalars of the 87C196KR JR
The 87C196JV JT A-step devices (JV-A JT-A) are the newest members of the MCS 96 microcontroller family
These devices are memory scalars of the 87C196JR D-step (JR-D) and are designed for strict functional and
electrical compatibility The JT-A has 32 Kbytes of on-chip EPROM 1 0 Kbytes of Register RAM and 512
bytes of Code RAM The JV-A has 48 Kbytes of on-chip EPROM 1 5 Kbytes of Register RAM and 512 bytes
of Code RAM
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 270827-006

1 page




87C196KR pdf
87C196KR KQ 87C196JV JT 87C196JR JQ
PIN DESCRIPTIONS
Symbol
Name and Function
VCC
VSS VSS VSS
Main supply voltage (a5V)
Digital circuit ground (0V) There are three VSS pins all of which MUST be
connected to a single ground plane
VREF
Reference for the A D converter (a5V) VREF is also the supply voltage to the
analog portion of the A D converter and the logic used to read Port 0 Must be
connected for A D and Port 0 to function
VPP
ANGND
XTAL1
Programming voltage for the EPROM parts It should be a12 5V for
programming It is also the timing pin for the return from powerdown circuit
Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC If this
function is not used VPP may be tied to VCC
Reference ground for the A D converter Must be held at nominally the same
potential as VSS
Input of the oscillator inverter and the internal clock generator
XTAL2
Output of the oscillator inverter
P2 7 CLKOUT
Output of the internal clock generator The frequency is the oscillator
frequency It has a 50% duty cycle Also LSIO pin
RESET
Reset input to the chip Input low for at least 16 state times will reset the chip The
subsequent low to high transition resynchronizes CLKOUT and commences a 10-
state time sequence in which the PSW is cleared bytes are read from 2018H and
201AH loading the CCBs and a jump to location 2080H is executed Input high for
normal operation RESET has an internal pullup
P5 7 BUSWIDTH
Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin
dynamically controls the Bus width of the bus cycle in progress If BUSWIDTH is
low an 8-bit cycle occurs If BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1
is ‘‘0’’ and CCR1 bit 2 is ‘‘1’’ all bus cycles are 8-bit if CCR bit 1 is ‘‘1’’ and CCR1
bit 2 is ‘‘0’’ all bus cycles are 16-bit CCR bit 1 e ‘‘0’’ and CCR1 bit 2 e ‘‘0’’ is
illegal Also an LSIO pin when not used as BUSWIDTH
NMI A positive transition causes a non-maskable interrupt vector through memory
location 203EH Used by Intel (GND this pin)
P5 1 INST
Output high during an external memory read indicates the read is an instruction
fetch INST is valid throughout the bus cycle INST is active only during external
memory fetches during internal EP ROM fetches INST is held low Also LSIO
when not INST
EA Input for memory select (External Access) EA equal to a high causes memory
accesses to locations 2000H through 5FFFH to be directed to on-chip EPROM
ROM EA equal to a low causes accesses to these locations to be directed to off-
chip memory EA e a12 5V causes execution to begin in the Programming
Mode EA latched at reset
P5 0 ALE ADV
Address Latch Enable or Address Valid output as selected by CCR Both pin
options provide a latch to demultiplex the address from the address data bus
When the pin is ADV it goes inactive (high) at the end of the bus cycle ADV can
be used as a chip select for external memory ALE ADV is active only during
external memory accesses Also LSIO when not used as ALE
5

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87C196KR arduino
87C196KR KQ 87C196JV JT 87C196JR JQ
AC CHARACTERISTICS (Over Specified Operating Conditions) (Continued)
Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns FOSC e 16 MHz
The 87C196KR KQ JV JT JR JQ will meet these specifications
Symbol
Parameter
Min
TRLCL
RD Low to CLKOUT
Falling Edge
4
TRLRH
TRHLH
RD Low Period
RD Rising Edge to
ALE ADV Rising Edge
TOSC b 5
TOSC
TRLAZ
TLLWL
RD Low to Address Float
ALE ADV Falling Edge
to WR Falling Edge
TOSC b 10
TCLWL
CLKOUT Low to
WR Falling Edge
b5
TQVWH
TCHWH
Data Stable to WR Rising Edge
CLKOUT High to WR
Rising Edge
TOSC b 23
b 10
TWLWH
TWHQX
TWHLH
WR Low Period
Data Hold after WR Rising Edge
WR Rising Edge to ALE ADV
Rising Edge
TOSC b 20
TOSC b 25
TOSC b 10
TWHBX
BHE INST Hold after WR
Rising Edge
TOSC b 10
TWHAX
TRHBX
TRHAX
AD8–15 Hold after WR Rising Edge
BHE INST Hold after RD Rising Edge
AD8–15 Hold after RD Rising Edge
TOSC b 30(4)
TOSC b 10
TOSC b 30(4)
Max
30
TOSC a 25
5
25
15
TOSC a 15
Units
ns
ns
ns(3)
ns(5)
ns
ns
ns
ns
ns
ns
ns(3)
ns
ns
ns
ns
NOTES
1 Testing performed at 4 0 MHz however the device is static by design and will typically operate below 1 Hz
2 Typical specifications not guaranteed
3 Assuming back-to-back bus cycles
4 8-bit bus only
5 TRLAZ (max) e 5 ns by design
11

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