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PDF 87C196KC Data sheet ( Hoja de datos )

Número de pieza 87C196KC
Descripción 16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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87C196KC
16-BIT HIGH-PERFORMANCE CHMOS
MICROCONTROLLER
Automotive
Y b40 C to a125 C
Y 16 Kbytes of On-Chip EPROM
Y 232 Byte Register File
Y Full Duplex Serial Port
Y High-Speed I O Subsystem
Y 16-Bit Timer
Y 256 Bytes of Additional RAM
Y 16-Bit Up Down Counter with Capture
Y Register-to-Register Architecture
Y 3 Pulse-Width-Modulated Outputs
Y 28 Interrupt Sources 16 Vectors
Y Four 16-Bit Software Timers
Y Peripheral Transaction Server
Y 1 75 ms 16 x 16 Multiply (16 MHz)
Y 3 0 ms 32 16 Divide (16 MHz)
Y Powerdown and Idle Modes
Y Five 8-Bit I O Ports
Y 16-Bit Watchdog Timer
Y Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y 8- or 10-Bit 8-Channel A D Converter
with Sample Hold
Y HOLD HLDA Bus Protocol
Y OTP One-Time Programmable and
QROM Versions
Y Available in 12 MHz and 16 MHz
Versions
Y 16 MHz Operation
The 87C196KC 16-bit microcontroller is a high-performance member of the MCS 96 microcontroller family
The 87C196KC is an enhanced 8XC196KB device with 488 bytes RAM 16 MHz operation and 16 Kbytes of
on-chip EPROM Intel’s CHMOS process provides a high performance processor along with low power con-
sumption
Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are
available for pulse or waveform generation The high-speed output can also generate four software timers or
start an A D conversion Events can be based on the timer or up down counter
NOTICE
This datasheet contains information on products in full production Specifications within this datasheet
are subject to change without notice Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
January 1995
Order Number 270846-004

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87C196KC pdf
AUTOMOTIVE 87C196KC
PIN DESCRIPTIONS
Symbol
Name and Function
VCC
VSS
VREF
Main supply voltage (5V)
Digital circuit ground (0V) There are three VSS pins all of which must be connected
Reference voltage for the A D converter (5V) VREF is also the supply voltage to the analog
portion of the A D converter and the logic used to read Port 0 Must be connected for A D
and Port 0 to function
ANGND
VPP
Reference ground for the A D converter Must be held at nominally the same potential as
VSS
Timing pin for the return from powerdown circuit Connect this pin with a 1 mF capacitor to
VSS and a 1 MX resistor to VCC If this function is not used VPP may be tied to VCC This pin
is the programming voltage on the EPROM device
XTAL1
Input of the oscillator inverter and of the internal clock generator
XTAL2
Output of the oscillator inverter
CLKOUT
Output of the internal clock generator The frequency of CLKOUT is the oscillator
frequency
RESET
Reset input to the chip
BUSWIDTH
Input for buswidth selection If CCR bit 1 is a one this pin selects the bus width for the bus
cycle in progress If BUSWIDTH is a 1 a 16-bit bus cycle occurs If BUSWIDTH is a 0 an
8-bit cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus
NMI A positive transition causes a vector through 203EH
INST
Output high during an external memory read indicates the read is an instruction fetch INST
is valid throughout the bus cycle INST is activated only during external memory accesses
and output low for a data fetch
EA Input for memory select (External Access) EA equal to a TTL-high causes memory
accesses to locations 2000H through 5FFFH to be directed to on-chip ROM EPROM EA
equal to a TTL-low causes accesses to those locations to be directed to off-chip memory
ALE ADV
Address Latch Enable or Address Valid output as selected by CCR Both pin options
provide a signal to demultiplex the address from the address data bus When the pin is
ADV it goes inactive high at the end of the bus cycle ALE ADV is activated only during
external memory accesses
RD Read signal output to external memory RD is activated only during external memory reads
WR WRL
Write and Write Low output to external memory as selected by the CCR WR will go low for
every external write while WRL will go low only for external writes where an even byte is
being written WR WRL is activated only during external memory writes
BHE WRH
Bus High Enable or Write High output to external memory as selected by the CCR BHE e
0 selects the bank of memory that is connected to the high byte of the data bus A0 e 0
selects the bank of memory that is connected to the low byte of the data bus Thus
accesses to a 16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the
high byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH function is
selected the pin will go low if the bus cycle is writing to an odd memory location BHE WRH
is valid only during 16-bit external memory write cycles
5

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87C196KC arduino
System Bus Timings
AUTOMOTIVE 87C196KC
270846 – 22
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