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PDF MMSF2P02E Data sheet ( Hoja de datos )
| Número de pieza | MMSF2P02E | |
| Descripción | SINGLE TMOS POWER MOSFET 2.5 AMPERES 20 VOLTS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMSF2P02E/D
™Designer's Data Sheet
Medium Power Surface Mount Products
TMOS Single P-Channel
Field Effect Transistors
MiniMOS™ devices are an advanced series of power MOSFETs
which utilize Motorola’s TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the drain–to–source diode
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dc–dc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
G
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs
• Miniature SO–8 Surface Mount Package — Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed
• Avalanche Energy Specified
• Mounting Information for SO–8 Package Provided
• IDSS Specified at Elevated Temperature
MMSF2P02E
Motorola Preferred Device
SINGLE TMOS
POWER MOSFET
2.5 AMPERES
20 VOLTS
RDS(on) = 0.250 OHM
™
D
S
CASE 751–05, Style 13
SO–8
N–C
Source
Source
Gate
18
27
36
45
Top View
Drain
Drain
Drain
Drain
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)(1)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C (2)
Drain Current — Continuous @ TA = 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TA = 25°C(2)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 20 Vdc, VGS = 5.0 Vdc, IL = 6.0 Apk, L = 12 mH, RG = 25 Ω)
Thermal Resistance — Junction to Ambient(2)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
VDSS
VGS
ID
ID
IDM
PD
TJ, Tstg
EAS
20
± 20
2.5
1.7
13
2.5
– 55 to 150
216
Vdc
Vdc
Adc
Apk
Watts
°C
mJ
RθJA
TL
50 °C/W
260 °C
DEVICE MARKING
S2P02
(1) Negative sign for P–Channel device omitted for clarity.
(2) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided), 10 sec. max.
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMSF2P02ER2
13″
12 mm embossed tape
2500 units
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a registered trademark of Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4
©MMoottoororolal,aInTc.M19O9S6 Power MOSFET Transistor Device Data
1
1 page  
di/dt = 300 A/µs
Standard Cell Density
trr
High Cell Density
trr
ta tb
100
VGS = 20 V
SINGLE PULSE
10 TC = 25°C
MMSF2P02E
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
thick single sided), 10s max.
1 ms
10 ms
1 dc
t, TIME
Figure 11. Reverse Recovery Time (trr)
250
200
0.1
0.01
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
100
ID = 6 A
150
100
50
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy
10
rating must be derated for temperature as shown in the ac-
companying graph (Figure 13). Maximum energy at currents
below rated continuous ID can safely be assumed to equal
the values indicated.
1 D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
0.01
0.001
1.0E–05
SINGLE PULSE
1.0E–04
1.0E–03
Normalized to θja at 10s.
Chip 0.0022 Ω 0.0210 Ω 0.2587 Ω 0.7023 Ω 0.6863 Ω
0.0020 F 0.0207 F
0.3517 F 3.1413 F
108.44 F Ambient
1.0E–02
1.0E–01
t, TIME (s)
1.0E+00
Figure 14. Thermal Response
1.0E+01
1.0E+02
1.0E+03
Motorola TMOS Power MOSFET Transistor Device Data
5
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