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PDF 83C554 Data sheet ( Hoja de datos )

Número de pieza 83C554
Descripción 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless/ 7 channel 10 bit A/D/ I2C/ PWM/ capture/compare/ high I/O/ 64L LQFP
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INTEGRATED CIRCUITS
80C554/83C554/87C554
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C,
PWM, capture/compare, high I/O, 64L LQFP
Preliminary specification
Replaces data of 1999 Apr 07
IC20 Data Handbook
2000 Nov 10
Philips
Semiconductors

1 page




83C554 pdf
Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
PIN DESCRIPTION
PIN NO.
MNEMONIC
LQFP
VDD
9
STADC
10
PWM0
PWM1
EW
P0.0-P0.7
11
12
13
54–61
P1.0-P1.7
23–30
23–28
29–30
23–26
27
28
29
30
P2.0-P2.7
43–50
P3.0-P3.7
31–38
31
32
33
34
35
36
37
38
TYPE
I
I
O
O
I
I/O
I/O
I/O
I/O
I
I
I
I/O
I/O
I/O
I/O
NAME AND FUNCTION
Digital Power Supply: Positive voltage power supply pin during normal operation, idle and
power-down mode.
Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be
started by software).
Pulse Width Modulation: Output 0.
Pulse Width Modulation: Output 1.
Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external program and data memory. In this application it uses
strong internal pull-ups when emitting 1s. Port 0 is also used to input the code byte during
programming and to output the code byte during verification.
Port 1: 8-bit I/O port. Alternate functions include:
(P1.0-P1.5): Programmable I/O port pins.
(P1.6, P1.7): Open drain port pins.
CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.
T2 (P1.4): T2 event input.
RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
SCL (P1.6): Serial port clock line I2C-bus.
SDA (P1.7): Serial port data line I2C-bus.
Port 1 has four modes selected on a per bit basis by writing to the P1M1 and P1M2 registers as
follows:
P1M1.x
0
0
1
1
P1M2.x
0
1
0
1
Mode Description
Pseudo–bidirectional (standard c51 configuration; default)
Push-Pull
High impedance
Open drain
Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.
Port 2: 8-bit programmable I/O port.
Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also used to
input the upper order address during EPROM programming and verification. A8 is on P2.0, A9 on
P2.1, through A13 on P2.5.
Port 2 has four output modes selected on a per bit basis by writing to the P2M1 and P2M2 registers
as follows:
P2M1.x
0
0
1
1
P2M2.x
0
1
0
1
Mode Description
Pseudo–bidirectional (standard c51 configuration; default)
Push-Pull
High impedance
Open drain
Port 3: 8-bit programmable I/O port. Alternate functions include:
RxD(P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt.
INT1 (P3.3): External interrupt.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
Port 3 has four modes selected on a per bit basis by writing to the P3M1 and P3M2 registers as
follows:
P3M1.x
0
0
1
1
P3M2.x
0
1
0
1
Mode Description
Pseudo–bidirectional (standard c51 configuration; default)
Push–Pull
High impedance
Open drain
2000 Nov 10
5

5 Page





83C554 arduino
Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
Expanded Data RAM Addressing
The 8xC554 has internal data memory that is mapped into four
separate segments: the lower 128 bytes of RAM, upper 128 bytes of
RAM, 128 bytes Special Function Register (SFR), and 256 bytes
expanded RAM (EXTRAM).
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are
directly and indirectly addressable.
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are
indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80H to FFH)
are directly addressable only.
4. The 256-bytes expanded RAM (ERAM, 00H – FFH) are indirectly
accessed by move external instruction, MOVX, and with the
EXTRAM bit cleared, see Figure 4.
The Lower 128 bytes can be accessed by either direct or indirect
addressing. The Upper 128 bytes can be accessed by indirect
addressing only. The Upper 128 bytes occupy the same address
space as the SFR. That means they have the same address, but are
physically separate from SFR space.
When an instruction accesses an internal location above address
7FH, the CPU knows whether the access is to the upper 128 bytes
of data RAM or to SFR space by the addressing mode used in the
instruction. Instructions that use direct addressing access SFR
space. For example:
MOV 0A0H,#data
accesses the SFR at location 0A0H (which is P2). Instructions that
use indirect addressing access the Upper 128 bytes of data RAM.
For example:
MOV @R0,#data
where R0 contains 0A0H, accesses the data byte at address 0A0H,
rather than P2 (whose address is 0A0H).
The ERAM can be accessed by indirect addressing, with EXTRAM
bit cleared and MOVX instructions. This part of memory is physically
located on-chip, logically occupies the first 256-bytes of external
data memory.
With EXTRAM = 0, the EXTRAM is indirectly addressed, using the
MOVX instruction in combination with any of the registers R0, R1 of
the selected bank or DPTR. An access to ERAM will not affect ports
P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during expanded
RAM addressing. For example, with EXTRAM = 0,
MOVX @R0,#data
where R0 contains 0A0H, accesses the ERAM at address 0A0H
rather than external memory. An access to external data memory
locations higher than FFH (i.e., 0100H to FFFFH) will be performed
with the MOVX DPTR instructions in the same way as in the
standard 80C51, so with P0 and P2 as data/address bus, and P3.6
and P3.7 as write and read timing signals. Refer to Figure 5.
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar
to the standard 80C51. MOVX @ Ri will provide an 8-bit address
multiplexed with data on Port 0 and any output port pins can be
used to output higher order address bits. This is to provide the
external paging capability. MOVX @DPTR will generate a 16-bit
address. Port 2 outputs the high-order eight address bits (the
contents of DPH) while Port 0 multiplexes the low-order eight
address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will
generate either read or write signals on P3.6 (#WR) and P3.7 (#RD).
The stack pointer (SP) may be located anywhere in the 256 bytes
RAM (lower and upper RAM) internal data memory. The stack may
not be located in the ERAM address space.
AUXR
Address = 8EH
Not Bit Addressable
Reset Value = xxxx x110B
— — — — — LVADC EXTRAM AO
Bit: 7 6 5 4 3 2 1 0
Symbol Function
AO Disable/Enable ALE
AO Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency.
1 ALE is active only during a MOVX or MOVC instruction.
EXTRAM
Internal/External RAM (00H – FFH) access using MOVX @Ri/@DPTR
EXTRAM
0
1
Operating Mode
Internal ERAM (00H–FFH) access using MOVX @Ri/@DPTR
External data memory access.
LVADC
Enable A/D low voltage operation
LVADC
0
1
Operating Mode
Turns off A/D charge pump.
Turns on A/D charge pump. Required for operation below 4V.
— Not implemented, reserved for future use*.
NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that
case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00979A
Figure 4. AUXR: Auxiliary Register
2000 Nov 10
11

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