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PDF NE556D Data sheet ( Hoja de datos )
| Número de pieza | NE556D | |
| Descripción | DUAL TIMING CIRCUIT | |
| Fabricantes | Motorola Inc | |
| Logotipo |  |
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Order this document by MC3456/D
Dual Timing Circuit
The MC3456 dual timing circuit is a highly stable controller capable of
producing accurate time delays, or oscillation. Additional terminals are
provided for triggering or resetting if desired. In the time delay mode of
operation, the time is precisely controlled by one external resistor and
capacitor per timer. For astable operation as an oscillator, the free running
frequency and the duty cycle are both accurately controlled with two external
resistors and one capacitor per timer. The circuit may be triggered and reset
on falling waveforms, and the output structure can source or sink up to
200 mA or drive MTTL circuits.
• Direct Replacement for NE556/SE556 Timers
• Timing from Microseconds through Hours
• Operates in Both Astable and Monostable Modes
• Adjustable Duty Cycle
• High Current Output can Source or Sink 200 mA
• Output can Drive MTTL
• Temperature Stability of 0.005% per °C
• Normally “On” or Normally “Off” Output
• Dual Version of the Popular MC1455 Timer
MC3456
DUAL TIMING CIRCUIT
SEMICONDUCTOR
TECHNICAL DATA
P SUFFIX
PLASTIC PACKAGE
CASE 646
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–14)
PIN CONNECTIONS
Figure 1. 22 Second Solid State Time Delay Relay Circuit
10 k
0.1 µF
5
0.01 µF
1.0 k
38
4
2 1/2
MC3456
6 R 20 M
7
MT2 Load
G MT1
1 1.0 µF C
–10 V
1N4003
t = 1.1; R and C = 22 sec
Time delay (t) is variable by
changing R and C (see Figure 16).
1N4740
3.5 k –
250 V
10
+
µF
Figure 3. General Test Circuit
Discharge A 1
Threshold A 2
Control A 3
Reset A 4
Output A 5
Trigger A 6
Gnd 7
14 VCC
13 Discharge B
12 Threshold B
11 Control B
10 Reset B
9 Output B
8 Trigger B
(Top View)
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC3456P
NE556D
0° to +70°C
Plastic DIP
SO–14
VR ICC VCC
+
0.01 µF
VO
Reset 4 8
700
5
Control
Voltage
VCC 7
Discharge
1/2
3
Output
ISink
ISource
MC3456
Gnd
12
Threshold
6 Ith
Trigger
2.0 k VS
2 (12)
Threshold
3 (11)
Control Voltage
Test circuit for measuring DC parameters (to set output and measure parameters):
wa) When VS 2/3 VCC, VO is low.
vb) When VS 1/3 VCC, VO is high.
c) When VO is low, Pin 7 sinks current. To test for Reset, set VO high,
c) apply Reset voltage, and test for current flowing into Pin 7. When Reset
c) is not in use, it should be tied to VCC.
6 (8)
Trigger
Figure 2. Block Diagram (1/2 Shown)
VCC
14
5k
+
Comp
–A
5k
+
Comp
–B
5k
Flip
R Flop
Q
S Inhibit/
Reset
1 (13)
Discharge
5 (9)
Output
7
Gnd
4 (10)
Reset
MOTOROLA ANALOG IC DEVICE DATA
© Motorola, Inc. 1996
Rev 2
1
1 page  
MC3456
Figure 13. 1/2 Representative Circuit Schematic
Control Voltage
Threshold
Comparator
VCC
Trigger
Comparator
Flip–Flop
Output
4.7 k
830 4.7 k
1.0 k
6.8 k
5.0 k
Threshold
10 k
7.0 k
cb
5.0 k e 4.7 k
3.9 k
cb
Output
Trigger
Reset
Discharge
Gnd
Reset
Discharge
100 k
100
5.0 k
220
4.7 k
GENERAL OPERATION
The MC3456 is a dual timing circuit which uses as its
timing elements an external resistor/capacitor network. It can
be used in both the monostable (one shot) and astable
modes with frequency and duty cycle, controlled by the
capacitor and resistor values. While the timing is dependent
upon the external passive components, the monolithic circuit
provides the starting circuit, voltage comparison and other
functions needed for a complete timing circuit. Internal to the
integrated circuit are two comparators, one for the input
signal and the other for capacitor voltage; also a flip–flop and
digital output are included. The comparator reference
voltages are always a fixed ratio of the supply voltage thus
providing output timing independent of supply voltage.
Monostable Mode
In the monostable mode, a capacitor and a single resistor
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode (refer to circuit Figure 15). When the input
voltage to the trigger comparator falls below 1/3 VCC the
comparator output triggers the flip–flop so that it’s output sets
low. This turns the capacitor discharge transistor “off” and
drives the digital output to the high state. This condition
allows the capacitor to charge at an exponential rate which is
set by the RC time constant. When the capacitor voltage
reaches 2/3 VCC the threshold comparator resets the
flip–flop. This action discharges the timing capacitor and
returns the digital output to the low state. Once the flip–flop
has been triggered by an input signal, it cannot be retriggered
until the present timing period has been completed. The time
that the output is high is given by the equation t = 1.1 RA C.
Various combinations of R and C and their associated times
are shown in Figure 14. The trigger pulse width must be less
than the timing period.
A reset pin is provided to discharge the capacitor thus
interrupting the timing cycle. As long as the reset pin is low,
the capacitor discharge transistor is turned “on” and prevents
the capacitor from charging. While the reset voltage is
applied the digital output will remain the same. The reset pin
should be tied to the supply voltage when not in use.
Figure 14. Time Delay
100
10
1.0
0.1
0.01
0.001
10 µs 100 µs 1.0 ms 10 ms 100 ms 1.0 10 100
td, TIME DELAY (s)
MOTOROLA ANALOG IC DEVICE DATA
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet NE556D.PDF ] | |
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