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PDF 82433LX Data sheet ( Hoja de datos )
| Número de pieza | 82433LX | |
| Descripción | LOCAL BUS ACCELERATOR (LBX) | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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82433LX 82433NX
LOCAL BUS ACCELERATOR (LBX)
Y Supports the Full 64-bit Pentium
Processor Data Bus at Frequencies up
to 66 MHz (82433LX and 82433NX)
Y Drives 3 3V Signal Levels on the CPU
Data and Address Buses (82433NX)
Y Provides a 64-Bit Interface to DRAM
and a 32-Bit Interface to PCI
Y Five Integrated Write Posting and Read
Prefetch Buffers Increase CPU and PCI
Performance
CPU-to-Memory Posted Write Buffer
4 Qwords Deep
PCI-to-Memory Posted Write Buffer
Two Buffers 4 Dwords Each
PCI-to-Memory Read Prefetch Buffer
4 Qwords Deep
CPU-to-PCI Posted Write Buffer
4 Dwords Deep
CPU-to-PCI Read Prefetch Buffer
4 Dwords Deep
Y CPU-to-Memory and CPU-to-PCI Write
Posting Buffers Accelerate Write
Performance
Y Dual-Port Architecture Allows
Concurrent Operations on the Host and
PCI Buses
Y Operates Synchronously to the CPU
and PCI Clocks
Y Supports Burst Read and Writes of
Memory from the Host and PCI Buses
Y Sequential CPU Writes to PCI
Converted to Zero Wait-State PCI
Bursts with Optional TRDY
Connection
Y Byte Parity Support for the Host and
Memory Buses
Optional Parity Generation for Host
to Memory Transfers
Optional Parity Checking for the
Secondary Cache
Parity Checking for Host and PCI
Memory Reads
Parity Generation for PCI to Memory
Writes
Y 160-Pin QFP Package
Two 82433LX or 82433NX Local Bus Accelerator (LBX) components provide a 64-bit data path between the
host CPU Cache and main memory a 32-bit data path between the host CPU bus and PCI Local Bus and a
32-bit data path between the PCI Local Bus and main memory The dual-port architecture allows concurrent
operations on the host and PCI Buses The LBXs incorporate three write posting buffers and two read prefetch
buffers to increase CPU and PCI performance The LBX supports byte parity for the host and main memory
buses The 82433NX is intended to be used with the 82434NX PCI Cache Memory Controller (PCMC) The
82433LX is intended to be used with the 82434LX PCMC During bus operations between the host main
memory and PCI the PCMC commands the LBXs to perform functions such as latching address and data
merging data and enabling output buffers Together these three components form a ‘‘Host Bridge’’ that
provides a full function dual-port data path interface linking the host CPU and PCI bus to main memory
This document describes both the 82433LX and 82433NX Shaded areas like this one describe the
82433NX operations that differ from the 82433LX
December 1995
Order Number 290478-004
1 page  
82433LX 82433NX
1 0 ARCHITECTURAL OVERVIEW
The 82430 PCIset consists of the 82434LX PCMC
and 82433LX LBX components plus either a PCI
ISA bridge or a PCI EISA bridge The 82430NX PCI-
set consists of the 82434NX PCMC and 82433NX
LBX components plus either a PCI ISA bridge or a
PCI EISA bridge The PCMC and LBX provide the
core cache and main memory architecture and
serves as the Host PCI bridge An overview of the
PCMC follows the system overview section
The Local Bus Accelerator (LBX) provides a high
performance data and address path for the
82430LX 82430NX PCIset The LBX incorporates
five integrated buffers to increase the performance
of the Pentium processor and PCI master devices
Two LBXs in the system support the following areas
1 64-bit data and 32-bit address bus of the Pentium
processor
2 32-bit multiplexed address data bus of PCI
3 64-bit data bus of the main memory
In addition the LBXs provide parity support for the
three areas noted above (discussed further in Sec-
tion 1 4)
1 1 Buffers in the LBX
The LBX components have five integrated buffers
designed to increase the performance of the Host
and PCI Interfaces of the 82430LX 82430NX
PCIset
With the exception of the PCI-to-Memory write buffer
and the CPU-to-PCI write buffer the buffers in the
LBX store data only addresses are stored in the
PCMC component
5
5 Page 
82433LX 82433NX
2 4 PCMC Interface Signals (Continued)
Signal Type
Description
EOL
t s End Of Line This signal is asserted when a PCI master read or write transaction is about
to overrun a cache line boundary The low order LBX will have this pin connected to the
PCMC (internally pulled up in the PCMC) The high order LBX connects this pin to a pull-
down resistor With one LBX EOL line being pulled down and the other LBX EOL pulled
up the LBX samples the value of this pin on the negation of the RESET signal to
determine if it’s the high or low order LBX
PPOUT t s
LBX PARITY This signal reflects the parity of the 16 AD lines driven from or latched into
the LBX depending on the command driven on PIG 3 0 The PCMC uses PPOUT from
both LBXs (called PPOUT 1 0 ) to calculate the PCI parity signal (PAR) for CPU to PCI
transactions during the address phase of the PCI cycle The LBX uses PPOUT to check
the PAR signal for PCI master transactions to memory during the address phase of the
PCI cycle When transmitting data to PCI the PCMC uses PPOUT to calculate the proper
value for PAR When receiving data from PCI the PCMC uses PPOUT to check the value
received on PAR
If the L2 cache does not implement parity the LBX will calculate parity so the PCMC can
drive the correct value on PAR during L2 reads initiated by a PCI master The LBX
samples the PPOUT signal at the negation of reset and compares that state with the state
of EOL to determine whether the L2 cache implements parity The PCMC internally pulls
down PPOUT 0 and internally pulls up PPOUT 1 The L2 supports parity if PPOUT 0 is
connected to the high order LBX and PPOUT 1 is connected to the low order LBX The
L2 is defined to not support parity if these connections are reversed and for this case the
LBX will calculate parity For normal operations either connection allows proper parity to
be driven to the PCMC
2 5 Reset and Clock Signals
Signal Type
Description
HCLK in
HOST CLOCK HCLK is input to the LBX to synchronize command and data from the host
and memory interfaces This input is derived from a buffered copy of the PCMC HCLKx
output
PCLK in
PCI CLOCK All timing on the LBX PCI interface is referenced to the PCLK input All
output signals on the PCI interface are driven from PCLK rising edges and all input signals
on the PCI interface are sampled on PCLK rising edges This input is derived from a
buffered copy of the PCMC PCLK output
RESET in
RESET Assertion of this signal resets the LBX After RESET has been negated the LBX
configures itself by sampling the EOL and PPOUT pins RESET is driven by the PCMC
CPURST pin The RESET signal is synchronous to HCLK and must be driven directly by
the PCMC
LP1 out LOOP 1 Phase Lock Loop Filter pin The filter components required for the LBX are
connected to these pins
LP2 in LOOP 2 Phase Lock Loop Filter pin The filter components required for the LBX are
connected to these pins
TEST in
TEST The TEST pin must be tied low for normal system operation
TSCON in
TRI-STATE CONTROL This signal enables the output buffers on the LBX This pin must
be held high for normal operation If TSCON is negated all LBX outputs will tri-state
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 82433LX.PDF ] | |
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