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PDF 82378ZB Data sheet ( Hoja de datos )

Número de pieza 82378ZB
Descripción SYSTEM I/O APIC(SIO.A) AND
Fabricantes Intel Corporation 
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82378ZB SYSTEM I/O (SIO) AND
82379AB SYSTEM I/O APIC (SIO.A)
Provides the Bridge Between the PCI
Bus and ISA Bus
100% PCI and ISA Compatible
PCI and ISA Master/Slave Interface
Directly Drives 10 PCI Loads and 6
ISA Slots
PCI at 25 MHz and 33 MHz
ISA from 6 MHz to 8.33 MHz
Enhanced DMA Functions
Scatter/Gather (S/G) (82378ZB)
Fast DMA Type A, B and F (82378ZB)
Compatible DMA Transfers
32-bit Addressability(82378ZB)
27-bit Addressability(82379AB)
Seven Independently Programmable
Channels
Functionality of Two 82C37A DMA
Controllers
Data Buffers to Improve Performance
8-Byte DMA/ISA Master Line Buffer
32-bit Posted Memory Write Buffer to
ISA
Integrated 16-bit BIOS Timer
Non-Maskable Interrupts (NMI)
PCI System Errors
ISA Parity Errors
Arbitration for ISA Devices
ISA Masters
DMA and Refresh
Four Dedicated PCI Interrupts
Level Sensitive
Mapped to Any Unused Interrupt
Arbitration for PCI Devices
Six PCI Masters Supported
Fixed, Rotating, or a Combination
Utility Bus (X-Bus) Peripheral Support
Provides Chip Select Decode
Controls Lower X-Bus Data Byte
Transceiver
Functionality of One 82C54 Timer
System Timer
Refresh Request
Speaker Tone Output
Functionality of Two 82C59 Interrupt
Controllers
14 Interrupts Supported
Edge/Level Selectable Interrupts
I/O APIC (Advanced Programmable
Interrupt Controller (82379AB)
Support for Multi-Processor Systems
System Power Management (Intel SMM
Support)
Programmable System Management
Interrupt (SMI)Hardware Events,
Software Events, EXTSMI#
Programmable CPU Clock Control
(STPCLK#)
Fast-On/Off Mode
208-Pin QFP Package
The 82378ZB System I/O (SIO) and 82379AB System I/O APIC (SIO.A) components are PCI-to-ISA Bus Bridge
devices. These devices integrate many of the common I/O functions found in today's ISA-based PC systemsa
seven channel DMA controller, two 82C59 interrupt controllers, an 8254 timer/counter, a BIOS timer, Intel SMM
power management support, and logic for NMI generation. In addition, the SIO and SIO.A each support a total of
six PCI Masters, and four PCI Interrupts. Decode is provided for peripheral devices such as the flash BIOS, real
time clock, keyboard/mouse controller, floppy controller, two serial ports, one parallel port, and IDE hard disk
drive.
For both the SIO and SIO.A, each DMA channel supports compatibility transfers. The SIO also supports types
A, B, and F transfers and scatter/gather. In addtion to the standard ISA-compatible interrupt controller that is in
both the SIO and SIO.A, the SIO.A contains an Advance Programmable Interrupt Controller (IO APIC) for use in
multi-processing systems.
This document describes both the 82378ZB (SIO) and 82379AB (SIO.A) components. Unshaded areas describe
the 82378ZB. Shaded areas, like this one, describe differences between the 82379AB and 82378ZB.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of
any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor
variations to this specification known as errata. Other brands and names are the property of their respective owners.
© INTEL CORPORATION 1996
March 1996
Order Number: 290571-001

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82378ZB pdf
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82378ZB (SIO) AND 82379 (SIO.A)
3.4.4. ICW3—INITIALIZATION COMMAND WORD 3 REGISTER ................................ ........................... 73
3.4.5. ICW4—INITIALIZATION COMMAND WORD 4 REGISTER ................................ ........................... 74
3.4.6. OCW1—OPERATIONAL CONTROL WORD 1 REGISTER ................................ ........................... 74
3.4.7. OCW2—OPERATIONAL CONTROL WORD 2 REGISTER ................................ ........................... 75
3.4.8. OCW3—OPERATIONAL CONTROL WORD 3 REGISTER ................................ ........................... 76
3.5. CONTROL REGISTERS ................................ ................................ ................................ ........................... 77
3.5.1. NMISC—NMI STATUS AND CONTROL REGISTER ................................ ................................ ..... 77
3.5.2. NMI ENABLE AND REAL-TIME CLOCK ADDRESS REGISTER ................................ .................. 78
3.5.3. PORT 92 REGISTER ................................ ................................ ................................ ......................... 78
3.5.4. DIGITAL OUTPUT REGISTER ................................ ................................ ................................ ......... 79
3.5.5. RESET UBUS IRQ1/IRQ12 REGISTER ................................ ................................ .......................... 79
3.5.6. COPROCESSOR ERROR REGISTER ................................ ................................ ............................ 80
3.5.7. ELCR—EDGE/LEVEL CONTROL REGISTER ................................ ................................ ............... 80
3.6. POWER MANAGEMENT REGISTERS ................................ ................................ ................................ ... 80
3.6.1. APMC—ADVANCED POWER MANAGEMENT CONTROL PORT ................................ .............. 81
3.6.2. APMS—ADVANCED POWER MANAGEMENT STATUS PORT ................................ .................. 81
3.7. APIC REGISTERS (82379AB ONLY) ................................ ................................ ................................ ...... 81
3.7.1. IOREGSEL—I/O REGISTER SELECT REGISTER (82379AB Only) ................................ ............ 82
3.7.2. IOWIN—I/O WINDOW REGISTER (82379AB Only) ................................ ................................ ....... 82
3.7.3. APICID—I/O APIC IDENTIFICATION REGISTER (82379AB Only) ................................ .............. 82
3.7.4. APICID—I/O APIC VERSION REGISTER (82379AB Only) ................................ ........................... 83
3.7.5. APICARB—I/O APIC ARBITRATION REGISTER (82379AB Only) ................................ ............... 83
3.7.6. IOREDTBL[15:0]—I/O REDIRECTION TABLE REGISTERS (82379AB Only) ............................. 83
4.0. FUNCTIONAL DESCRIPTION .................................................................................................................... 86
4.1. MEMORY AND I/O ADDRESS MAP ................................ ................................ ................................ ....... 86
4.1.1. MEMORY ADDRESS MAP (GENERATING MEMCS#) ................................ ................................ . 86
4.1.2. BIOS MEMORY SPACE ................................ ................................ ................................ .................... 87
4.1.3. I/O ACCESSES ................................ ................................ ................................ ................................ .. 87
4.1.4. SUBTRACTIVELY DECODED CYCLES TO ISA ................................ ................................ ............ 88
4.1.5. UTILITY BUS ENCODED CHIP SELECTS ................................ ................................ ..................... 88
4.2. PCI INTERFACE ................................ ................................ ................................ ................................ ....... 88
4.2.1. PCI COMMAND SET ................................ ................................ ................................ ......................... 88
4.2.2. TRANSACTION TERMINATION ................................ ................................ ................................ ....... 89
4.3. PCI ARBITRATION CONTROLLER ................................ ................................ ................................ ........ 90
4.3.1. ARBITRATION SIGNAL PROTOCOL ................................ ................................ .............................. 90
4.3.2. INTERNAL/EXTERNAL ARBITER CONFIGURATION ................................ ................................ ... 91
4.3.3. Guaranteed Access Time Mode ................................ ................................ ................................ ........ 92
4.3.3.1. DMA LATENCIES IN GAT MODE ONLY (82378ZB ONLY) ................................ .................... 92
4.4. ISA INTERFACE ................................ ................................ ................................ ................................ ....... 92
4.4.1. ISA CLOCK GENERATION ................................ ................................ ................................ ............... 93
4.5. DMA CONTROLLER ................................ ................................ ................................ ................................ . 93
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82378ZB arduino
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82378ZB (SIO) AND 82379 (SIO.A)
Advanced Programmable Interrupt Controller (APIC) (SIO.A Only)
In addition to the standard ISA-compatible interrupt controller described above, the SIO.A incorporates the
Advanced Programmable Interrupt Controller (APIC). While the standard interrupt controller is intended for use in
a uni-processor system, APIC can be used in either a uni-processor or multi-processor system. APIC provides
multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt distribution
across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of
interrupts.
Power Management
Extensive power management capability permits a system to operate in a low power state without being
powered down. Once in the low power state (called 'Fast-Off' state), the computer appears to be off. For
example, the System Memory Management (SMM) code could turn off the CRT, line printer, hard disk drive's
spindle motor, and fans. In addition, the CPU's clock can be governed. To the user, the machine appears to be
in the off state. However, the system is actually in an extremely low power state that still permits the CPU to
function and maintain communication connections normally associated with today's desktops (e.g., LAN,
Modem, or FAX). Programmable options provide power management flexibility. For example, various system
events can be programmed to place the system in the low power state or break events can be programmed to
wake the system up.
Test
The test block provides the interface to the test circuitry within the SIO/SIO.A. The test input can be used to tri-
state all of the SIO/SIO.A outputs.
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