PDF 82374EB Data sheet ( Hoja de datos )

Número de pieza	82374EB
Descripción	SYSTEM COMPONENT (ESC)
Fabricantes	Intel Corporation
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No Preview Available ! 82374EB 82374SB EISA SYSTEM COMPONENT (ESC) Y Integrates EISA Compatible Bus Controller Translates Cycles Between EISA and ISA Bus Supports EISA Burst and Standard Cycles Supports ISA Zero Wait-State Cycles Supports Byte Assembly Disassembly for 8- 16- and 32-Bit Transfers Supports EISA Bus Frequency of up to 8 33 MHz Y Supports Eight EISA Slots Directly Drives Address Data and Control Signals for Eight Slots Decodes Address for Eight Slot Specific AENs Y Provides Enhanced DMA Controller Provides Scatter-Gather Function Supports Type A Type B Type C (Burst) and Compatible DMA Transfer Provides Seven Independently Programmable Channels Integrates Two 82C37A Compatible DMA Controllers Y Integrates the Functionality of two 82C59 Interrupt Controllers and two 82C54 Timers Provides 14 Programmable Channels for Edge or Level Interrupts Provides 4 PCI Interrupts Routible to any of 11 Interrupt Channels Supports Timer Function for Refresh Request System Timer Speaker Tone Fail Safe Timer and CPU Speed Control Y Advanced Programmable Interrupt Controller (APIC) Multiprocessor Interrupt Management Separate Bus For Interrupt Messages Y 5V CMOS Technology Y Provides High Performance Arbitration Supports Eight EISA Masters and PCEB Supports ISA Masters DMA Channels and Refresh Provides Programmable Arbitration Scheme for Fixed Rotating or Combination Priority Y Integrates Support Logic for X-Bus Peripherals Generates Chip Selects Encoded Chip Selects for Floppy and Keyboard Controller IDE Parallel Serial Ports and General Purpose Peripherals Provides Interface for Real Time Clock Generates Control Signals for X-Bus Data Transceiver Integrates Port 92 Mouse Interrupt and Coprocessor Error Reporting Y Generates Non-Maskable Interrupts (NMI) PCI System Errors PCI Parity Errors EISA Bus Parity Errors Fail Safe Timer Bus Timeout Via Software Control Y Provides BIOS Interface Supports 512K Bytes of Flash or EPROM BIOS on the X-Bus Allows BIOS on PCI Supports Integrated VGA BIOS Y 82374SB System Power Management (Intel SMM Support) Fast On Off Support via SMI GenerationHardware Events Software Events EXTSMI Fast Off Timer System Events Programmable CPU Clock Control Enables Energy Efficient Desktop Systems Y Only Available as Part of a Supported Kit Y 208-Pin QFP Package Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1996 March 1996 Order Number 290476-004 1 page CONTENTS PAGE 3 1 6 CLKDIV EISA CLOCK DIVISOR REGISTER 40 3 1 7 PCSA PERIPHERAL CHIP SELECT A REGISTER 41 3 1 8 PCSB PERIPHERAL CHIP SELECT B REGISTER 42 3 1 9 EISAID 4 1 EISA ID REGISTERS 43 3 1 10 SGRBA SCATTER GATHER RELOCATE BASE ADDRESS REGISTER 43 3 1 11 APICBASE APIC BASE ADDRESS RELOCATION 44 3 1 12 PIRQ 0 3 PIRQ ROUTE CONTROL REGISTERS 44 3 1 13 GPCSLA 2 0 GENERAL PURPOSE CHIP SELECT LOW ADDRESS REGISTER 45 3 1 14 GPCSHA 2 0 GENERAL PURPOSE CHIP SELECT HIGH ADDRESS REGISTER 45 3 1 15 GPCSM 2 0 GENERAL PURPOSE CHIP SELECT MASK REGISTER 46 3 1 16 GPXBC GENERAL PURPOSE PERIPHERAL X-BUS CONTROL REGISTER 46 3 1 17 PAC PCI APIC CONTROL REGISTER 47 3 1 18 TESTC TEST CONTROL REGISTER 47 3 1 19 SMICNTL SMI CONTROL REGISTER 47 3 1 20 SMIEN SMI ENABLE REGISTER 48 3 1 21 SEE SYSTEM EVENT ENABLE REGISTER 49 3 1 22 FTMR FAST OFF TIMER REGISTER 50 3 1 23 SMIREQ SMI REQUEST REGISTER 50 3 1 24 CTLTMR CLOCK SCALE STPCLK LOW TIMER 52 3 1 25 CTLTMRH CLOCK SCALE STPCLK HIGH TIMER 52 3 2 DMA Register Description 52 3 2 1 DCOM COMMAND REGISTER 52 3 2 2 DCM DMA CHANNEL MODE REGISTER 54 3 2 3 DCEM DMA CHANNEL EXTENDED MODE REGISTER 55 3 2 4 DR DMA REQUEST REGISTER 58 3 2 5 MASK REGISTER WRITE SINGLE MASK BIT 58 3 2 6 WAMB WRITE ALL MASK BITS REGISTER 59 3 2 7 DS DMA STATUS REGISTER 60 3 2 8 DB CA DMA BASE AND CURRENT ADDRESS REGISTER (8237 COMPATIBLE SEGMENT) 61 3 2 9 DB CBW DMA BASE AND CURRENT BYTE WORD COUNT REGISTER (8237 COMPATIBLE SEGMENT) 62 3 2 10 DMA BASE AND CURRENT HIGH BYTE WORD COUNT REGISTER DMA BASE HIGH BYTE WORD COUNT REGISTER 63 3 2 11 DMA MEMORY LOW PAGE REGISTER DMA MEMORY BASE LOW PAGE REGISTER 64 3 2 12 DMAP DMA PAGE REGISTER 64 5 5 Page 82374EB 82374SB 1 0 ARCHITECTURAL OVERVIEW The PCI-EISA bridge chip set provides an I O subsystem core for the next generation of high-performance personal computers (e g those based on the Intel486TM or Pentium processors) System designers can take advantage of the power of the PCI (Peripheral Component Interconnect) for the local I O bus while maintain- ing access to the large base of EISA and ISA expansion cards and corresponding software applications Extensive buffering and buffer management within the PCI-EISA bridge ensures maximum efficiency in both bus environments The chip set consists of two components the 82375EB SB PCI-EISA Bridge (PCEB) and the 82374EB SB EISA System Component (ESC) These components work in tandem to provide an EISA I O subsystem interface for personal computer platforms based on the PCI standard This section provides an overview of the PCI and EISA Bus hierarchy followed by an overview of the PCEB and ESC components Bus Hierarchy Concurrent Operations Figure 1 shows a block diagram of a typical system using the PCI-EISA Bridge chip set The system contains three levels of buses structured in the following hierarchy Host Bus as the execution bus PCI Bus as a primary I O bus EISA Bus as a secondary I O bus This bus hierarchy allows concurrency for simultaneous operations on all three bus environments Data buffer- ing permits concurrency for operations that cross over into another bus environment For example a PCI device could post data into the PCEB permitting the PCI Local Bus transaction to complete in a minimum time and freeing up the PCI Local Bus for further transactions The PCI device does not have to wait for the transfer to complete to its final destination Meanwhile any ongoing EISA Bus transactions are permitted to complete The posted data is then transferred to its EISA Bus destination when the EISA Bus is available The PCI-EISA Bridge chip set implements extensive buffering for PCI-to-EISA and EISA-to-PCI bus transactions In addition to concurrency for the operations that cross bus environments data buffering allows the fastest operations within a particular bus environment (via PCI burst transfers and EISA burst transfers) The PCI Local Bus with 132 MByte sec and EISA with 33 MByte sec peak data transfer rate represent bus environments with significantly different bandwidths Without buffering transfers that cross the single bus environment are performed at the speed of the slower bus Data buffers provide a mechanism for data rate adoption so that the operation of the fast bus environment (PCI) i e usable bandwidth is not significantly impacted by the slower bus environment (EISA) 11 11 Page

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