DataSheet.es    


PDF 82371SB Data sheet ( Hoja de datos )

Número de pieza 82371SB
Descripción 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



Hay una vista previa y un enlace de descarga de 82371SB (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! 82371SB Hoja de datos, Descripción, Manual

E
82371FB (PIIX) AND 82371SB (PIIX3)
PCI ISA IDE XCELERATOR
n Bridge Between the PCI Bus and ISA Bus
n PCI and ISA Master/Slave Interface
PCI from 25–33 MHz
ISA from 7.5–8.33 MHz
5 ISA Slots
n Fast IDE Interface
Supports PIO and Bus Master IDE
Supports up to Mode 4 Timings
Transfer Rates to 22 MB/Sec
8 x 32-Bit Buffer for Bus Master IDE PCI
Burst Transfers
Separate Master/Slave IDE Mode
Support (PIIX3)
n Plug-n-Play Port for Motherboard Devices
2 Steerable DMA Channels (PIIX Only)
Fast DMA with 4-Byte Buffer (PIIX Only)
2 Steerable Interrupts Lines on the PIIX
and 1 Steerable Interrupt Line on the
PIIX3
1 Programmable Chip Select
n Steerable PCI Interrupts for PCI Device Plug-
n-Play
n PCI Specification Revision 2.1 Compliant
(PIIX3)
n Functionality of One 82C54 Timer
System Timer; Refresh Request;
Speaker Tone Output
n Two 82C59 Interrupt Controller Functions
14 Interrupts Supported
Independently Programmable for
Edge/Level Sensitivity
n Enhanced DMA Functions
Two 8237 DMA Controllers
Fast Type F DMA
Compatible DMA Transfers
7 Independently Programmable
Channels
n X-Bus Peripheral Support
Chip Select Decode
Controls Lower X-Bus Data Byte
Transceiver
n I/O Advanced Programmable Interrupt
Controller (IOAPIC) Support (PIIX3)
n Universal Serial Bus (USB) Host Controller
(PIIX3)
Compatible with Universal Host
Controller Interface (UHCI)
Contains Root Hub with 2 USB Ports
n System Power Management (Intel SMM
Support)
Programmable System Management
Interrupt (SMI)—Hardware Events,
Software Events, EXTSMI#
Programmable CPU Clock Control
(STPCLK#)
Fast On/Off Mode
n Non-Maskable Interrupts (NMI)
PCI System Error Reporting
n NAND Tree for Board-Level ATE Testing
n 208-Pin QFP
The 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerators are multi-function PCI devices
implementing a PCI-to-ISA bridge function and an PCI IDE function. In addition, the PIIX3 implements a
Universal Serial Bus host/hub function. As a PCI-to-ISA bridge, the PIIX/PIIX3 integrates many common I/O
functions found in ISA-based PC systems—a seven-channel DMA controller, two 82C59 interrupt controllers,
an 8254 timer/counter, and power management support. In addition to compatible transfers, each DMA
channel supports type F transfers. Chip select decoding is provided for BIOS, real time clock, and keyboard
controller. Edge/Level interrupts and interrupt steering are supported for PCI plug and play compatibility. The
PIIX/PIIX3 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks
and CD ROMs. The PIIX/PIIX3 provides motherboard plug and play compatibility. PIIX implements two
steerable DMA channels (including type F transfers) and up to two steerable interrupt lines. PIIX3 implements
one steerable interrupt line. The interrupt lines can be routed to any of the available ISA interrupts. Both
PIIX/PIIX3 implement a programmable chip select.
PIIX3 contains a Universal Serial Bus (USB) Host Controller that is UHCI compatible. The Host Controller’s
root hub has two programmable USB ports. PIIX3 also provides support for an external IOAPIC.
This document describes the PIIX3 Component. Unshaded areas describe the 82371FB PIIX. Shaded areas,
like this one, describe the PIIX3 operations that differ from the 82371FB PIIX.
© INTEL CORPORATION 1996, 1997
April 1997
Order Number: 290550-002

1 page




82371SB pdf
E
82371FB (PIIX) AND 82371SB (PIIX3)
2.5.1.9. DMA Memory Low Page Registers ....................................................................................... 65
2.5.1.10. DMA Clear Byte Pointer Register........................................................................................ 66
2.5.1.11. DMC—DMA Master Clear Register..................................................................................... 66
2.5.1.12. DCLM—DMA Clear Mask Register ..................................................................................... 66
2.5.2. TIMER/COUNTER REGISTER DESCRIPTION .......................................................................... 66
2.5.2.1. TCW—Timer Control Word Register..................................................................................... 66
2.5.2.2. Interval Timer Status Byte Format Register .......................................................................... 68
2.5.2.3. Counter Access Ports Register ............................................................................................. 69
2.5.3. INTERRUPT CONTROLLER REGISTERS ................................................................................. 69
2.5.3.1. ICW1—Initialization Command Word 1 Register................................................................... 70
2.5.3.2. ICW2—Initialization Command Word 2 Register................................................................... 70
2.5.3.3. ICW3—Initialization Command Word 3 Register................................................................... 71
2.5.3.4. ICW3—Initialization Command Word 3 Register................................................................... 71
2.5.3.5. ICW4—Initialization Command Word 4 Register................................................................... 71
2.5.3.6. OCW1—Operational Control Word 1 Register ...................................................................... 72
2.5.3.7. OCW2—Operational Control Word 2 Register ...................................................................... 72
2.5.3.8. OCW3—Operational Control Word 3 Register ...................................................................... 73
2.5.3.9. ELCR1—Edge/Level Triggered Register............................................................................... 74
2.5.3.10. ELCR2—Edge/Level Triggered Register............................................................................. 74
2.5.4. X-BUS, COPROCESSOR, and RESET REGISTERS ................................................................. 75
2.5.4.1. Reset X-Bus IRQ12 And IRQ1 Register................................................................................ 75
2.5.4.2. Coprocessor Error Register .................................................................................................. 75
2.5.4.3. RC—Reset Control Register ................................................................................................. 75
2.5.5. NMI REGISTERS ........................................................................................................................ 76
2.5.5.1. NMISC—NMI Status And Control Register ........................................................................... 76
2.5.5.2. NMI Enable and Real-Time Clock Address Register............................................................. 77
2.6. System Power Management Registers .............................................................................................. 77
2.6.1. APMC—ADVANCED POWER MANAGEMENT CONTROL PORT ............................................. 77
2.6.2. APMS—ADVANCED POWER MANAGEMENT STATUS PORT ................................................ 78
2.7. PCI BUS Master IDE Registers.......................................................................................................... 78
2.7.1. BMICOM—BUS MASTER IDE COMMAND REGISTER ............................................................. 78
2.7.2. BMISTA—BUS MASTER IDE STATUS REGISTER ................................................................... 79
2.7.3. BMIDTP—BUS MASTER IDE DESCRIPTOR TABLE POINTER REGISTER ............................. 80
2.8. USB I/O Registers.............................................................................................................................. 80
2.8.1. USBCMDUSB Command Register........................................................................................... 80
2.8.2. USBSTSUSB Status Register.................................................................................................. 82
2.8.3. USBINTRUSB Interrupt Enable Register ................................................................................. 83
2.8.4. FRNUMFrame Number Register.............................................................................................. 83
2.8.5. FLBASEADDFrame List Base Address Register...................................................................... 84
2.8.6. Start Of Frame (SOF) Modify Register ........................................................................................ 84
2.8.7. PORTSCPort Status and Control Register ............................................................................... 85
3.0. FUNCTIONAL DESCRIPTION .............................................................................................................. 89
5

5 Page





82371SB arduino
E
82371FB (PIIX) AND 82371SB (PIIX3)
Signal Name
MIRQ0/IRQ0
(PIIX3 Only)
MIRQ[1:0]
(PIIX Only)
Type
I/O
I
Description
MOTHERBOARD DEVICE INTERRUPT REQUEST: The MIRQx
signals can be internally connected to interrupts IRQ[15,14,12:9,7:3].
Each MIRQx line has a separate Route Control Register. If MIRQx and
PIRQx# are steered to the same ISA interrupt, the device connected to
the MIRQx should produce active high, level interrupts. The
MIRQ0/IRQ0 signal has two functions (for PIIX3 only), depending on
the programming of the IRQ0 Enable bit (MIRQ0 Register). In the
systems that include the PIIX3 and IOAPIC, the MIRQ0/IRQ0 pin will
function as the IRQ0 output and should be connected to the INTIN2
input of the IOAPIC. The interrupt from the Secondary IDE Channel
should be connected to the IRQ15 input on PIIX3 and to the INTIN15
input on the IOAPIC. In the systems that include the PIIX3 only, the
interrupt from the Secondary IDE Channel should be connected to the
MIRQ0/IRQ0 input.
If an MIRQ line is steered to a given IRQ input to the internal 8259, the
corresponding ISA IRQ is masked, unless the Route Control register is
programmed to allow the interrupts to be shared. This should only be
done if the device connected to the MIRQ line and the device
connected to the ISA IRQ line both produce active high, level
interrupts.
MIRQ0 can be configured as an output to connect the internal IRQ0
signal to an external IO-APIC.
1.3. IDE Interface Signals
Signal Name
DD[15:0]/
PCS#,
SBHE#,
SA[19:8]
APICCS#
(PIIX3)
DIOR#
DIOW#
DDRQ[1:0]
DDAK[1:0]#
Type
I/O
O
I/O
I/O
O
Description
DISK DATA: These signals directly drive the corresponding signals on
up to two IDE connectors (primary and secondary). In addition, these
signals are buffered (using 2xALS245’s on the motherboard) to produce
the SA[19:8], PCS#, and SBHE# signals (see separate descriptions).
For the PIIX3, DD14 is buffered to produce APICCS#
O DISK I/O READ: This signal directly drives the corresponding signal on
up to two IDE connectors (primary and secondary).
O DISK I/O WRITE: This signal directly drives the corresponding signal on
up to two IDE connectors (primary and secondary).
I DISK DMA REQUEST: These input signals are directly driven from the
DRQ signals on the primary (DDRQ0) and secondary (DDRQ1) IDE
connectors. They are used in conjunction with the PCI Bus master IDE
function and are not associated with any ISA-Compatible DMA channel.
O DISK DMA ACKNOWLEDGE: These signals directly drive the DAK#
signals on the primary (DDAK0# ) and secondary (DDAK1#) IDE
connectors. These signals are used in conjunction with the PCI Bus
master IDE function and are not associated with any ISA-Compatible
DMA channel.
11

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet 82371SB.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
82371SB82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATORIntel Corporation
Intel Corporation

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar