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PDF 82371AB Data sheet ( Hoja de datos )

Número de pieza 82371AB
Descripción PCI-TO-ISA / IDE XCELERATOR PIIX4
Fabricantes Intel Corporation　
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E
82371AB PCI-TO-ISA / IDE
XCELERATOR (PIIX4)
Supported Kits for both Pentium® and
Pentium® II Microprocessors
82430TX ISA Kit
82440LX ISA/DP Kit
Multifunction PCI to ISA Bridge
Supports PCI at 30 MHz and 33 MHz
Supports PCI Rev 2.1 Specification
Supports Full ISA or Extended I/O
(EIO) Bus
Supports Full Positive Decode or
Subtractive Decode of PCI
Supports ISA and EIO at 1/4 of PCI
Frequency
Supports both Mobile and Desktop
Deep Green Environments
3.3V Operation with 5V Tolerant
Buffers
Ultra-low Power for Mobile
Environments Support
Power-On Suspend, Suspend to
RAM, Suspend to Disk, and Soft-
OFF System States
All Registers Readable and
Restorable for Proper Resume
from 0.V Suspend
Power Management Logic
Global and Local Device
Management
Suspend and Resume Logic
Supports Thermal Alarm
Support for External
Microcontroller
Full Support for Advanced
Configuration and Power Interface
(ACPI) Revision 1.0 Specification
and OS Directed Power
Management
Integrated IDE Controller
Independent Timing of up to
4 Drives
PIO Mode 4 and Bus Master IDE
Transfers up to 14 Mbytes/sec
Supports “Ultra DMA/33”
Synchronous DMA Mode Transfers
up to 33 Mbytes/sec
Integrated 16 x 32-bit Buffer for IDE
PCI Burst Transfers
Supports Glue-less “Swap-Bay”
Option with Full Electrical Isolation
Enhanced DMA Controller
Two 82C37 DMA Controllers
Supports PCI DMA with 3 PC/PCI
Channels and Distributed DMA
Protocols (Simultaneously)
Fast Type-F DMA for Reduced PCI
Bus Usage
Interrupt Controller Based on Two
82C59
15 Interrupt Support
Independently Programmable for
Edge/Level Sensitivity
Supports Optional I/O APIC
Serial Interrupt Input
Timers Based on 82C54
System Timer, Refresh Request,
Speaker Tone Output
USB
Two USB 1.0 Ports for Serial
Transfers at 12 or 1.5 Mbit/sec
Supports Legacy Keyboard and
Mouse Software with USB-based
Keyboard and Mouse
Supports UHCI Design Guide
SMBus
Host Interface Allows CPU to
Communicate Via SMBus
Slave Interface Allows External
SMBus Master to Control Resume
Events
Real-Time Clock
256-byte Battery-Back CMOS SRAM
Includes Date Alarm
Two 8-byte Lockout Ranges
Microsoft Win95* Compliant
324 mBGA Package
© INTEL CORPORATION 1997
April 1997
Order Number: 290562-001
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)

1 page




82371AB pdf
E
82371AB (PIIX4)
4.1.6. CLASSC—Class Code Register (Function 0) .....................................................................................56
4.1.7. HEDT—Header Type Register (Function 0)........................................................................................56
4.1.8. IORT—ISA I/O Recovery Timer Register (Function 0) .......................................................................56
4.1.9. XBCS—X-Bus Chip Select Register (Function 0) ...............................................................................57
4.1.10. PIRQRC[A:D]—PIRQX Route Control Registers (Function 0) .........................................................59
4.1.11. SERIRQC—Serial IRQ Control Register (Function 0) ......................................................................59
4.1.12. TOM—Top of Memory Register (Function 0) ....................................................................................60
4.1.13. MSTAT—Miscellaneous Status Register (Function 0)......................................................................61
4.1.14. MBDMA[1:0]—Motherboard Device DMA Control Registers (Function 0)........................................61
4.1.15. APICBASE—APIC Base Address Relocation Register (Function 0)................................................62
4.1.16. DLC—Deterministic Latency Control Register (Function 0)..............................................................62
4.1.17. PDMACFG—PCI DMA Configuration Register (Function 0).............................................................63
4.1.18. DDMABP—Distributed DMA Slave Base Pointer Registers (Function 0).........................................64
4.1.19. GENCFG—General Configuration Register (Function 0) .................................................................65
4.1.20. RTCCFG—Real Time Clock Configuration Register (Function 0) ....................................................67
4.2. PCI to ISA/EIO Bridge IO Space Registers (IO) ........................................................................................68
4.2.1. DMA Registers.....................................................................................................................................68
4.2.1.1. DCOM—DMA Command Register (IO)........................................................................................68
4.2.1.2. DCM—DMA Channel Mode Register (IO)....................................................................................69
4.2.1.3. DR—DMA Request Register (IO).................................................................................................70
4.2.1.4. WSMB—Write Single Mask Bit (IO) .............................................................................................70
4.2.1.5. RWAMB—Read/Write All Mask Bits (IO) .....................................................................................71
4.2.1.6. DS—DMA Status Register (IO) ....................................................................................................71
4.2.1.7. DBADDR—DMA Base and Current Address Registers (IO) .......................................................72
4.2.1.8. DBCNT—DMA Base and Current Count Registers (IO)..............................................................72
4.2.1.9. DLPAGE—DMA Low Page Registers (IO)...................................................................................73
4.2.1.10. DCBP—DMA Clear Byte Pointer Register (IO)..........................................................................73
4.2.1.11. DMC—DMA Master Clear Register (IO) ....................................................................................73
4.2.1.12. DCLM—DMA Clear Mask Register (IO).....................................................................................74
4.2.2. Interrupt Controller Registers...............................................................................................................74
4.2.2.1. ICW1—Initialization Command Word 1 Register (IO) ..................................................................74
4.2.2.2. ICW2—Initialization Command Word 2 Register (IO) ..................................................................75
4.2.2.3. ICW3—Initialization Command Word 3 Register (IO) ..................................................................75
4.2.2.4. ICW3—Initialization Command Word 3 Register (IO) ..................................................................76
4.2.2.5. ICW4—Initialization Command Word 4 Register (IO) ..................................................................76
4.2.2.6. OCW1—Operational Control Word 1 Register (IO)......................................................................77
4.2.2.7. OCW2—Operational Control Word 2 Register (IO)......................................................................77
4.2.2.8. OCW3— Operational Control Word 3 Register (IO).....................................................................78
4.2.2.9. ELCR1—Edge/Level Control Register (IO) ..................................................................................79
4.2.2.10. ELCR2—Edge/Level Control Register (IO) ................................................................................79
4.2.3. Counter/Timer Registers......................................................................................................................80
4.2.3.1. TCW—Timer Control Word Register (IO).....................................................................................80
4.2.3.2. TMRSTS—Timer Status Registers (IO) .......................................................................................82
PRELIMINARY
5
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)

5 Page





82371AB arduino
E
82371AB (PIIX4)
11.4. Suspend/Resume and Power Plane Control ..........................................................................................228
11.4.1. System Suspend..............................................................................................................................228
11.4.2. System Resume ..............................................................................................................................230
11.4.3. System Suspend and Resume Control Signaling............................................................................232
11.4.3.1. Power Supply Timings ..............................................................................................................232
11.4.3.2. Power Level Active Status Signal Timings ...............................................................................233
11.4.3.3. Power Management Signal Timings (Powered From Suspend Power Well) ...........................234
11.4.3.4. PCI Clock Stop and Start Timing Relationships .......................................................................235
11.4.3.5. Power Management Signal Timings (Powered From PIIX4 Main Core Well) ..........................236
11.4.3.6. Power Management Signal Timings (Powered From PIIX4 Main Core Well) ..........................238
11.4.3.7. Mechanical Off to On Condition Timings ..................................................................................240
11.4.3.8. On State to Power On Suspend State Timing ..........................................................................242
11.4.3.9. Power On Suspend to On Timing (With a Full System Reset).................................................244
11.4.3.10. System Transition From Power On Suspend to On (With Only Processor Reset)................246
11.4.3.11. Power On Suspend to On Timing (With No Resets) ..............................................................248
11.4.3.12. On State to Suspend to RAM State Timing ............................................................................250
11.4.3.13. Suspend-To-RAM to On Timing (With Full System Reset) ....................................................252
11.4.3.14. On State to Suspend to Disk/Soft Off State Timings..............................................................254
11.4.3.15. Suspend-To-Disk to On (With Full System Reset).................................................................256
11.4.4. Shadow Registers............................................................................................................................258
11.5. System Management..............................................................................................................................262
11.5.1. SMI Operation..................................................................................................................................262
11.5.2. SMI# Generation Events..................................................................................................................263
11.5.3. Global Standby Timer Operation .....................................................................................................265
11.5.4. SMBus Functional Description ........................................................................................................266
11.5.4.1. SMBus Host Interface...............................................................................................................266
11.5.4.2. SMBus Slave Interface .............................................................................................................267
11.6. ACPI Support..........................................................................................................................................268
11.6.1. SCI Generation ................................................................................................................................268
11.6.2. Power Management Timer...............................................................................................................268
11.6.3. Global Lock......................................................................................................................................269
12.0. PINOUT INFORMATION ...........................................................................................................................270
13.0. PIIX4 PACKAGE INFORMATION.............................................................................................................274
14.0. TESTABILITY ............................................................................................................................................277
14.1. Test Mode Description............................................................................................................................277
14.2. Tri-state Mode.........................................................................................................................................278
14.3. NAND Tree Mode ...................................................................................................................................278
PRELIMINARY
11
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)

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